Post Code Reference Tables - Acer Aspire 8943G Series Service Manual

Post Code Reference Tables

These tables describe the POST codes and descriptions during the POST.
Post Code Range
Phase
SEC
PEI
DXE
BDS
SMM
S3
ASL
PostBDS
InsydeH2ODDT™
Reserve
OEM Reserve
Reserved
SEC Phase POST Code Table
Functionality Name (Include\
PostCode.h)
SEC_SYSTEM_POWER_ON
SEC_BEFORE_MICROCODE_PATCH
SEC_AFTER_MICROCODE_PATCH
SEC_ACCESS_CSR
SEC_GENERIC_MSRINIT
SEC_CPU_SPEEDCFG
SEC_SETUP_CAR_OK
SEC_FORCE_MAX_RATIO
SEC_GO_TO_SECSTARTUP
SEC_GO_TO_PEICORE
PEI Phase POST Code Table:
Functionality Name (Include\
PostCode.h)
PEI_SIO_INIT
PEI_CPU_REG_INIT
PEI_PCIE_MMIO_INIT
PEI_NB_REG_INIT
PEI_SB_REG_INIT
PEI_TPM_INIT
PEI_SMBUS_INIT
Chapter 4
POST Code Range
0x01 - 0x0F
0x70 - 0x9F
0x40 - 0x6F
0x10 - 0x3F
0xA0 - 0xBF
0xC0 - 0xCF
0x51 – 0x55
0xE1 – 0xE4
0xF9 – 0xFE
0xD0 – 0xD7
0xE8 – 0xEB
0xD8 – 0xE0
0xE5 – 0xE7
0xEC – 0xF8
Post
Phase
Code
SEC 1
SEC 2
SEC 3
SEC 4
SEC 5
SEC 6
SEC 7
SEC 8
SEC 9
SEC 0A
Post
Phase
Code
PEI 70
PEI 71
PEI 74
PEI 75
PEI 76
PEI 78
PEI 79
Description
CPU power on and switch to
Protected mode
Patching CPU microcode
Setup Cache as RAM
PCIE MMIO Base Address initial
CPU Generic MSR initialization
Setup CPU speed
Cache as RAM test
Tune CPU frequency ratio to
maximum level
Setup BIOS ROM cache
Enter Boot Firmware Volume
Description
Super I/O Initialization
CPU Early Initialization
PCIE MMIO BAR Initialization
North Bridge Early Initialization
South Bridge Early Initialization
TPM Initialization
SMBUS Early Initialization
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