Item
Hardware Features
22
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Meets Microsoft WLP (Windows Logo Program) audio requirements
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High performance DACs with digital >110dB and analog 98dB (A-
weighting) signal-to-noise
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High performance ADCs with digital > 100dB and analog 90dB (A-
Weighting) signal-to-noise ratio
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Six DAC channels support 16/20/24-bit PCM format for 5.1 sound
playback
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Two stereo ADCs support 16/20/24-bit PCM format, multiple stereo
recording
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All DACs supports 44.1k/48k/96k/192kHz sample rate
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All ADCs supports 44.1k/48k/96k/192kHz sample rate
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Primary 16/20/24-bit SPDIF-OUT supports 32k/44.1k/48k/88.2k/96k/
192kHz sample rate
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Secondary 16/20/24-bit SPDIF-OUT supports 32k/44.1k/48k/88.2k/
96k/192kHz sample rate
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Analog jacks (port-A, B, C, E and G) support stereo input and output
re-tasking
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Support MONO output at port-H
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Port-A/D/E/F built in headphone amplifiers
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Port-E and Port-F headphone amplifiers can drive earphone directly
without DC blocking capacitor
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Port-B/C/E/F with software selectable boost gain (+10/+20/+30dB)
for analog microphone input
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Supports external PCBEEP input and built-in digital BEEP generator
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Software selectable 2.5V/3.2V VREFOUT
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Supports legacy analog mixer architecture
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Four channels of digital microphone array input for voice applications
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Two jack detection pins each designed to detect up to 4 jacks
plugging
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1.0dB/step playback volume control
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1.5dB/step recording volume control
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High pass filter to cancel DC offset from AD converter
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Jack detection function is supported when device is in power down
mode (D3)
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2 GPIOs (General Purpose Input and Output) for customized
applications. GPIO0 and GPIO1 share pin with digital microphone
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Supports anti-pop mode when analog power AVDD is on and digital
power is off.
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Audio Content Protection for Blu-Ray DVD playback (with selected
player provided by InterVideo,
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CyberLink and ArcSoft)
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Intel low power ECR compliant and power status control for every
analog converter and pin widgets
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Supports 3.3V digital core power, 1.5V~ 3.3V scalable digital I/O
power for HD Audio link, and 3.0~5.0V analog power
Specification
Chapter 1