Harman Kardon AVR-134 Service Manual page 20

No . Pin Name I/O
40 NC
41 RO UT 3
42 NC
43 LO UT 2
44 NC
45 RO UT 2
46 NC
47 LO UT 1
48 NC
49 RO UT 1
50 NC
51 LI N
52 RI N
53 VC OM
54 VR EF H-
55 A VDD
56 AV SS
57 RX 0
58 NC
59 RX 1
60 TE ST 1I
61 RX 2
62 NC
63 RX 3
64 PV SS
65 R
66 P VDD
67 RX 4
68 TE ST 2I
69 RX 5
70 C AD0
71 RX 6
72 C AD1
73 RX 7I
74 I2CI
75 D AUX2
76 VI NI
77 MC LK
78 TX0
79 TX 1
80 IN T0
No te : A ll in put pins except internal biased pins and internal pull -down pin should not be left fl oating.
No Co nnect pin
-
No internal bonding . Th is pin should be opened.
O DA C3 Rc h An alog Ou tput Pi n
No Co nnect pin
-
No internal bonding . Th is pin should be opened.
OD AC 2 Lc h An alog Ou tput Pin
No Co nnect pin
-
No internal bonding . Th is pin should be opened.
O DA C2 Rc h An alog Ou tput Pi n
No Co nnect pin
-
No in ternal bondin g. Th is pin should be opened.
OD AC 1 Lc h An alog Ou tput Pin
No Co nnect pin
-
No internal bonding . Th is pin should be opened.
O DA C1 Rc h An alog Ou tput Pi n
No Co nnect pin
-
No internal bonding . Th is pin should be opened.
IL ch An alog Input Pin
I Rc h An alog Input Pin
Co mmon Vo ltage Ou tput Pin
-
2.2F capacitor should be connected to AV SS externally.
Po siti ve Vo ltage Re ference Input Pin , AVDD
- An alog Power Supply Pin, 4.5V~ 5.5V
An alog Gr ound Pin, 0V
-
I R eceiver Chan nel 0 Pi n (Internal biased pin. Internally biased at PV DD/ 2)
No Co nnect pin
-
No internal bondi ng. Th is pin should be connected to PV SS.
I R eceiver Chan nel 1 Pi n (Internal biased pin. Internally biased at PV DD/ 2)
Test 1 Pi n
Th is pin should be connected to PV SS.
I R eceiver Chan nel 2 Pi n (Internal biased pin. Internally biased at PV DD/ 2)
No Co nnect pin
-
No internal bondi ng. Th is pin should be connected to PV SS.
I R eceiver Chan nel 3 Pi n (Internal biased pin. Internally biased at PV DD/ 2)
-P LL Gr ound pin
Ex ternal Re sistor Pi n
-
12k +/-1% resistor should be connected to PV SS externally.
-
PL L Po wer supply Pin, 4.5V~ 5.5V
I R eceiver Chan nel 4 Pi n (Internal biased pin. Internally biased at PV DD/ 2)
Test 2 Pi n
Th is pin should be connected to PV SS.
I R eceiver Chan nel 5 Pi n (Internal biased pin. Internally biased at PV DD/ 2)
Ch ip A ddress 0 Pi n (ADC/ DAC part)
I
I R eceiver Chan nel 6 Pi n (Internal biased pin. Internally biased at PV DD/ 2)
Ch ip A ddress 1 Pi n (ADC/ DAC part)
I
R eceiver Chan nel 7 Pi n (Internal biased pin. Internally biased at PV DD/ 2)
Co ntrol Mo de Sele ct Pin.
"L": 4-wi re Seri al, "H": I 2 C Bu s
I Au xi li ary Au di o Data Input Pin (D IR/D IT part)
V-bit Input Pin for Transmitter Ou tput
Ma ster Cl ock Input Pin
I
OT ransmit Ch annel (T hrough Data) Ou tput 0 Pi n
Transmit Ch annel Ou tput1 pin
O Wh en TX bit = "0 ", Transmit Ch annel (T hrough Data) Ou tput 1 Pi n.
Wh en TX bit = "1 ", Transmit Ch annel (DAUX2 Data) Ou tput Pi n (Def ault ).
OI nterrupt 0 Pin
Function
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