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SIGNAL NAME
AHCLKR0/AHCLKR1
ACLKR0
AFSR0
AHCLKX0/AHCLKX2
ACLKX0
AFSX0
AMUTE0
AXR0[0]
AXR0[1]
AXR0[2]
AXR0[3]
AXR0[4]
AXR0[5]/ SPI1_SCS
AXR0[6]/SPI1_ENA
AXR0[7]/SPI1_CLK
AXR0[8]/AXR1[5]/
SPI1_SOMI
AXR0[9]/AXR1[4]/
SPI1_SIMO
AXR0[10]/AXR1[3]
AXR0[11]/AXR1[2]
AXR0[12]/AXR1[1]
AXR0[13]/AXR1[0]
AXR0[14]/AXR2[1]
AXR0[15]/AXR2[0]
ACLKR1
AFSR1
AHCLKX1
ACLKX1
AFSX1
AMUTE1
SPI0_SOMI/I2C0_SDA
SPI0_SIMO
SPI0_CLK/I2C0_SCL
SPI0_SCS/I2C1_SCL
SPI0_ENA /I2C1_SDA
OSCIN
OSCOUT
OSCV
DD
OSCV
SS
CLKIN
PLLHV
RESET
PIN
(1)
TYPE
PULL
NO.
McASP0, McASP1, McASP2, and SPI1 Serial Ports
143
IO
-
139
IO
-
141
IO
-
2
IO
-
142
IO
-
144
IO
-
3
O
-
113
IO
-
115
IO
-
116
IO
-
117
IO
-
119
IO
-
120
IO
-
121
IO
-
122
IO
-
126
IO
-
127
IO
-
130
IO
-
131
IO
-
134
IO
-
135
IO
-
137
IO
-
138
IO
-
9
IO
-
12
IO
-
5
IO
-
7
IO
-
11
IO
-
4
O
-
SPI0, I2C0, and I2C1 Serial Port Pins
111
IO
-
110
IO
-
108
IO
-
107
IO
-
105
IO
-
23
I
-
24
O
-
25
PWR
-
22
PWR
-
17
I
-
27
PWR
-
Device Reset
14
I
-
(2)
(3)
GPIO
Y
McASP0 and McASP1 ReceiveMasterClock
Y
McASP0 ReceiveBit Clock
Y
McASP0 ReceiveFrameSync(L/RClock)
Y
McASP0 and McASP2 Transmit MasterClock
Y
McASP0 Transmit Bit Clock
Y
McASP0 TransmitFrame Sync(L/RClock)
Y
McASP0 MUTE Output
Y
McASP0 SerialData0
Y
McASP0 SerialData1
Y
McASP0 SerialData2
Y
McASP0 SerialData3
Y
McASP0 SerialData4
Y
McASP0 SerialData5 or SPI1 SlaveChip Select
Y
McASP0 SerialData6 or SPI1 Enable(Ready)
Y
McASP0 SerialData7 or SPI1 SerialClock
McASP0 SerialData8 or McASP1 SerialData5 or
Y
SPI1 DataPin SlaveOutMasterIn
McASP0 SerialData9 or McASP1 SerialData4 or
Y
SPI1 DataPin SlaveInMasterOut
Y
McASP0 SerialData10 or McASP1 SerialData3
Y
McASP0 SerialData11 or McASP1 SerialData2
Y
McASP0 SerialData12 or McASP1 SerialData1
Y
McASP0 SerialData13 or McASP1 SerialData0
Y
McASP0 SerialData14 or McASP2 SerialData1
Y
McASP0 SerialData15 or McASP2 SerialData0
Y
McASP1 ReceiveBit Clock
Y
McASP1 ReceiveFrameSync(L/RClock)
Y
McASP1 Transmit Master Clock
Y
McASP1 Transmit Bit Clock
Y
McASP1 Transmit Frame Sync(L/RClock)
Y
McASP1 MUTE Output
Y
SPI0 DataPin SlaveOutMasterInor I2C0SerialData
Y
SPI0 DataPin SlaveInMasterOut
Y
SPI0 SerialClockor I2C0SerialClock
Y
SPI0 SlaveChip Selector I2C1SerialClock
Y
SPI0 Enable(Ready)or I2C1SerialData
Clocks
N
1.2-VOscillator Input
N
1.2-VOscillator Output
N
Oscillator 1.2-VV
N
Oscillator V
N
Alternate clock input (3.3-V LVCMOS Input)
N
PLL 3.3-VSupplyInput(requiresexternalfilter)
N
Deviceresetpin
16
DESCRIPTION
tappoint(forfilteronly)
DD
tappoint(forfilteronly)
SS
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