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QQ
3 7 63 1515 0
Pin No.
Pin Name
54
55
56
57
58
59
60
UNI SCK
61
Z MUTE
62
NOSE SW
63
FLASH W
64
65 to 70
71
72 to 76
77
78
79
80
81
82
TE
83
OSCOUT
L 13942296513
84
85
CYRIL SEL
86
DEMOSEL
87
88
SYSRST
89, 90
91
92
CDMON
93 to 95
96
97
98
99
100
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.
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I/O
BUIN
I
Back-up power supply detect signal input
NCO
O
Not used. (Open)
AEP, UK model: RDS (Radio Data System) data block synchronized detect
DAVN
I
signal input
NCO
O
Not used. (Open)
UNISI
I
SONY bus data signal input
UNISO
O
SONY bus data signal output
O
SONY bus clock signal output
I
Mute signal input
I
Front panel attachment detect signal input
Memory mode change signal input
I
"L": flash write mode
SIRCS
I
Remote control signal input
NCO
O
Not used. (Open)
RC IN1
I
Rotary commander shift key signal input
NCO
O
Not used. (Open)
RESET
I
CPU reset signal input
NCO
O
Not used. (Open)
XIN
I
Low speed operation clock signal input (32.768 kHz)
XOUT
O
Low speed operation clock signal output (32.768 kHz)
VSS1
—
Ground pin
OSCIN
I
High speed operation clock signal input (18.432 MHz)
O
High speed operation clock signal output (18.432 MHz)
VCC3
—
Power supply pin (+3.3 V)
I
Cyril correspondence discrimination signal input
I
DEMO select signal input
FL ON
O
Fluorescent indicator tube power on signal output
O
System reset signal output
NCO
O
Not used. (Open)
CDON
I
CD mechanism servo power supply control request signal input
I
CD mechanism deck power supply control request signal input
NCO
O
Not used. (Open)
BUSON
O
Bus on signal output
TESTIN
I
Test mode detect signal input
AEP, UK model: Telephone attenuate detect signal input
TELATT
I
US, Canadian, E model: Not used.
ACCIN
I
Accessory power supply detect signal input
ATT
O
Audio mute control signal output
x
ao
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i
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8
Pin Description
US, Canadian, E model: Not used.
Q Q
3
6 7
1 3
"H": DEMO on, "L": DEMO off
u163
.
CDX-GT315C
2 9
9 4
2 8
"L": With panel, "H": Without panel
Normally "H": Single chip mode, after reset
1 5
0 5
8
2 9
9 4
"L": No correspondence
m
co
9 9
2 8
9 9
31
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