Sony PRS-500 Service Manual page 42

PRS-500
Pin No. Pin Name
J12 VSS
J13 TST3
J14 H_D5
J15 H_D4
K1 A16
K2 A15
K3 F_NRST
K4 VSS
K12 VSS
K13 TST2
K14 H_D3
K15 H_D2
L1 A20
L2 A17
L3 A21
L4 VDD
L12 VSS
L13 NPOR
L14 H_D1
L15 H_D0
M1 VDD
M2 A19
M3 F_RDY
M4 VDD
M5 VSS
M6 VSS
M7 VDD
M8 n.c.
M9 VSS
M10 VSS
M11 n.c.
M12 VDD
M13 BORDER0
M14 H_ACK
M15 H_DS
N1 D0
N2 VSS
N3 D2
N4 VDD
N5 BIST_EN
N6 F_NWE
N7 n.c.
N8 VSS
N9 VDD
N10 VSS
N11 CLK
N12 CLK_OUT
N13 COM_CTRL
N14 PWR_NEG
42
I/O
— Ground
I AutOmode (normal = "0")(Not used (Fixed to "L"))
I/O 8 bits data bus for main CPU
I/O 8 bits data bus for main CPU
O 22 bits address bus
O 22 bits address bus
O N reset for Flash
— Ground
— Ground
I Test mode (normal = "0")(Not used (Fixed to "L"))
I/O 8 bits data bus for main CPU
I/O 8 bits data bus for main CPU
O Not used (Open)
O 22 bits address bus
O Not used (Open)
— +3V0
— Ground
I Power on reset
I/O 8 bits data bus for main CPU
I/O 8 bits data bus for main CPU
— +3V0
O Not used (Open)
I Ready for Flash
— +3V0
— Ground
— Ground
— +3V0
— Not used (Open)
— Ground
— Ground
— Not used
— +3V0
O Border control
O Acknowledge for main CPU
I Device select from main CPU
I/O 32 bits data bus
— Ground
I/O 32 bits data bus
— +3V0
I Bist enable (Not used (Fixed to "L"))
O Write enable for Flash
— Not used (Open)
— Ground
— +3V0
— Ground
I Clock input
O Clock output
O Common control
O Negative power
Description