Pin No.
Pin Name
D4
VDD
D5
VDD
D6
VSS
D7
VSS
D8
n.c.
D9
VSS
D10
VSS
D11
VDD
D12
VSS
D13
VDD
D14
SRC_OE
D15
GT_SPV
E1
A4
E2
A5
E3
D16
E4
VSS
E5
n.c.
E12
VSS
E13
SRC_CL
E14
GT_MODE
E15
GT_CKV
F1
A6
F2
A7
F3
F_NOE
F4
VSS
F12
n.c.
F13
TST0
F14
GT_CASC
F15
H_NRST
G1
A8
G2
A9
G3
A10
G4
VSS
G12
VSS
G13
VDD
G14
H_CD
G15
H_WUP
H1
A12
H2
A11
H3
VDD
H4
n.c.
H12
n.c.
H13
VDD
H14
H_D7
H15
H_D6
J1
A14
J2
A13
J3
A18
J4
VSS
I/O
—
+3V0
—
+3V0
—
Ground
—
Ground
—
Not used (Open)
—
Ground
—
Ground
—
+3V0
—
Ground
—
+3V0
O
Output enable for source driver
O
Start signal for gate driver
O
22 bits address bus
O
22 bits address bus
I/O
32 bits data bus
—
Ground
—
Not used (Open)
—
Ground
O
Clock for source driver
O
Mode select for gate driver
O
Clock for gete driver
O
22 bits address bus
O
22 bits address bus
O
Output enable for Flash
—
Ground
—
Not used (Open)
I
Test mode (normal = "0")(Not used (Fixed to "L"))
O
CAS select for gate driver
I
Reset from main CPU
O
22 bits address bus
O
22 bits address bus
O
22 bits address bus
—
Ground
—
Ground
—
+3V0
I
Command/Data from main CPU
I
Wakeup from main CPU
O
22 bits address bus
O
22 bits address bus
—
+3V0
—
Not used (Open)
—
Not used (Open)
—
+3V0
I/O
8 bits data bus for main CPU
I/O
8 bits data bus for main CPU
O
22 bits address bus
O
22 bits address bus
O
22 bits address bus
—
Ground
Description
PRS-500
41