Sony HCD-VX555J Service Manual page 56

HCD-VX555/VX555J
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• IC502 M30622MGA-A45FP (CD MECHANISM CONTROLLER) (VIDEO BOARD)
Pin No. Pin Name I/O
1 SENSE I
2 SENSE CLK O
3 RESOLUTION O
4 CHROMA LEVEL O
5 DSP CLK O
6 TSENS —
7 REMOTE IN —
8 BYTE I
9 CN VSS —
10 DSP MUTE O
11 CTRL1 O
12 XRESET I
13 XOUT O
14 VSS —
15 XIN I
16 VCC —
17 NMI I
18 SCOR I
19 DSENS —
20 CL680INTERRUPT I
21 H.SYNC IN I
TE
22 L 13942296513 BGP O
23 —
24 PWM3(BD) O
25 —
26 PWM2(BD) O
27 —
28 PWM1(BD) O
29 12C.CLK I/O
30 12C.DATA I/O
31 DATA1O O
32 DATA1I I
33 CLK1 O
34 RTS1 O
35 DATAO O
36 DATAI I
37 CLK1 I
38 P.ON —
39 BUS XRDY I
40 BUS —
41 BUS XHOLD I
42, 43 BUS —
44 OSD.LANGUAGE I
45 VSYNC I
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46 BUS XWRL O
47 LO.BOOST —
48 AUDIO MUTE —
.
49 LOAD OUT —
50 LOAD IN —
51 INSW —
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Internal status (SENSE) signal input from the CXD3068Q (IC101)
Sense serial data reading clock signal output to the CXD3068Q (IC101)
Y resolution output
Chroma level output
Serial data transfer clock signal output to the CXD3068Q (IC101)
Not used (open)
Not used (open)
External data bus line byte selection signal input "L": 16 bit, "H": 8 bit (fixed at "L")
Ground terminal
Muting on/off control signal output to the CXD3068Q (IC101) "H": muting on
Clock selection signal output to the CXD3068Q (IC101) "L": 16.9344 MHz (double speed), "H": 33.8688 MHz
Reset signal input from the system controller (IC501) "L": reset
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
Main system clock output terminal (10 MHz)
Ground terminal
Main system clock input terminal (10 MHz)
Power supply terminal (+5V)
Non-maskable interrupt input terminal (fixed at "H" in this set)
Subcode sync (S0+S1) detection signal input from the CXD3068Q (IC101)
Not used (open)
Interrupt request signal input from the CL680 (IC505)
Horizontal sync signal input
Burst gate pulse signal output
Not used (open)
PWM3 signal output to the CXA2581N (IC103)
Not used (open)
PWM2 signal output to the CXA2581N (IC103)
Not used (open)
PWM1 signal output to the CXA2581N (IC103)
I 2 C clock signal
I 2 C data signal
Serial data output to the FLASH writer
Serial data input from the FLASH writer
Serial data transfer clock signal output to the FLASH writer
RTS signal to the FLASH writer
Serial data0 output to the CL680 (IC505)
Serial data0 input from the CL680 (IC505)
Data reading clock signal input from the CL680 (IC505)
Not used (open)
Ready signal input terminal Not used (fixed at "H")
Not used (open)
Hold signal input terminal from the FLASH writer
Not used (open)
OSD language select input terminal "H": English, "L": China
Vertical sync signal input
Bus write signal output to the FLASH writer
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Not used (open)
y
Not used (open)
i
Not used (open)
Not used (open)
Not used (fixed at "H")
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Description
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