Outline Of Circuit Description - Nikon COOLPIX S550 Repair Manual

1. OUTLINE OF CIRCUIT DESCRIPTION

1-1. CCD CIRCUIT DESCRIPTION
1. IC Configuration
The CCD peripheral circuit block basically consists of the fol-
lowing ICs.
IC913 (ICX665SQC) CCD imager
IC905 (ADDI7000BCPZRL) CDS, AGC, A/D converter,
IC901 (LR366877) V driver
2. IC913 (CCD)
Interline type CCD image sensor
Optical size 1/2.3 type
Effective pixels 3264 (H) x 2448 (V)
Pixels in total 3336 (H) x 2484 (V)
Optical black
Horizontal (H) direction: Front 6 pixels, Rear 39 pixels
Vertical (V) direction: Front 12 pixels, Rear 2 pixels
Dummy bit number Horizontal : 14
V
6
Pin 20
Fig. 1-1.Optical Black Location (Top View)
Pin No.
Symbol
øSUB Substrate clock
1
2 Protection transistor bias
V
L
3
øVOG
Vertical register end stage control clock
4
øLV Vertical - holizontal shift clock
5
VGND Pixel area GND
6 Vertical register transfer clock
Vø
1A
Vø Vertical register transfer clock
7
1B
8 Vø
Vertical register transfer clock
2
9
Vø Vertical register transfer clock
3A
10 Vø Vertical register transfer clock
3B
11 Vø
Vertical register transfer clock
3C
12
Vø Vertical register transfer clock
4
13 Vø Vertical register transfer clock
5A
14 Vø
Vertical register transfer clock
5B
15
Vø Vertical register transfer clock
5C
16 Vø Vertical register transfer clock
6S1
17
Vø Vertical storage control clock 2
6S2
18 Vø Vertical storage control clock 2
ST2
19 Vø Vertical storage control clock 1
ST1
H driver
Pin 1
2
12
H
39
Pin Description
Table 1-1. CCD Pin Description
- E･ S550 -
Fig. 1-2. CCD Block Diagram
Pin No.
Symbol
20
V
OUT
21
V
DD
22
NC
23
øRG
24 NC
25 AGND
26 AGND
27
HGND
28 CSUB
29 SUB_CONT Substrate bias control
30 NC
31 NC
32 NC
33 øLH1
34 øH1
35 øH2
36 øH3
37 Vø
HLD1
38 Vø
HLD2
– 2 –
INC
VMA21024-R.3750.A
Pin Description
Signal output
Circuit power
NC
Reset gate clock
NC
Circuit GND
Circuit GND
Horizontal transfer register GND
Substrate bias
NC
NC
NC
Horizontal register end stage transfer clock
Horizontal register transfer clock
Horizontal register transfer clock
Horizontal register transfer clock
Vertical signal hold clock 1
Vertical signal hold clock 2