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ZL6100EVAL2Z Dual Channel Evaluation Board
Description
The ZL6100 is an integrated mixed-signal power
conversion and management IC that combines an
efficient step-down DC/DC converter with key power and
thermal management functions in a single package. The
ZL6100 incorporates current sharing and adaptive
efficiency-optimization algorithms to provide a flexible,
efficient power IC building block.
The ZL6100EVAL2Z platform is a 6-layer board with two
power rails. One rail is a single phase, 30A power rail.
The other rail is a dual phase, 60A power rail
demonstrating the current sharing capability of the
ZL6100.
A USB to SMBus adapter board can be used to connect
the eval board to a PC. The PMBus command set is
accessed by using the Zilker Labs PowerNavigator™
evaluation software from a PC running Microsoft
Windows.
SYNC
DDC
SMBus
TRACK
September 11, 2009
AN1507.0
Application Note 1507
V IN
P3
EN
SYNC
SMBus
DDC
ENABLE
SW1
EN
SYNC
SMBus
DDC
EN
SYNC
SMBus
DDC
J1 0
VTRK
FIGURE 1. ZL6100EVAL2Z BLOCK DIAGRAM
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774
Features
• 30A Single-phase and 60A Dual-phase Rails
• Optimized for Efficiency
• Configurable Through SMBus
• Onboard Enable Switch
• Power Good Indicators
Target Specifications
• V
= 12V
IN
• V
= 1.8V/60A max
OUT1
• V
= 1.5V/30A max
OUT2
• f
= 300kHz
sw
• Efficiency: 90% at 50% load
• Output Ripple: ±1.5%
• Dynamic response: ±3%
(50%-70%-50% load step, di/dt = 2.5A/µs)
• Board Temperature: +25°C
ZL6100
ZL6100
ZL6100
PG
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Author: Marty Pandola
P1
V OUT2
P2
V OUT1
J1 1
SYNC
DDC
SMBus
PG
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Related Manuals for Intersil ZL6100EVAL2Z
Summary of Contents for Intersil ZL6100EVAL2Z
- Page 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. September 11, 2009 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc. AN1507.0 Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
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Page 2: Functional Description
(PG) LEDs indicate the correct state of PG when external 5. Set ENABLE switch to “ENABLE” power is applied to the ZL6100EVAL2Z board. (Note: If a 6. Monitor ZL6100EVAL2Z board operation using an USB board is connected to the ZL6100EVAL2Z and no... - Page 3 Board Schematics FIGURE 2. ZL6100EVAL2Z 60A CURRENT SHARING RAIL (PHASE A) CIRCUIT...
- Page 4 Board Schematics (Continued) FIGURE 3. ZL6100EVAL2Z 60A CURRENT SHARING RAIL (PHASE B) CIRCUIT...
- Page 5 Board Schematics (Continued) FIGURE 4. ZL6100EVAL2Z 30A SINGLE PHASE RAIL CIRCUIT...
- Page 6 Board Schematics (Continued) FIGURE 5. ZL6100EVAL2Z INTERFACE CIRCUITRY...
- Page 7 Board Schematics (Continued) FIGURE 6. POWER-IN CIRCUIT...
- Page 8 Board Schematics (Continued) FIGURE 7. PG LED CIRCUITRY...
- Page 9 Board Schematics (Continued) FIGURE 8. ENABLE SWITCH DEBOUNCE CIRCUIT FIGURE 9. ADDRESS SELECTION CIRCUITRY...
- Page 10 Application Note 1507 Board Layout – 6 Layers FIGURE 10. PCB – TOP LAYER AN1507.0 September 11, 2009...
- Page 11 Application Note 1507 Board Layout – 6 Layers (Continued) FIGURE 11. PCB – INNER LAYER 1 (VIEWED FROM TOP) AN1507.0 September 11, 2009...
- Page 12 Application Note 1507 Board Layout – 6 Layers (Continued) FIGURE 12. PCB – INNER LAYER 2 (VIEWED FROM TOP) AN1507.0 September 11, 2009...
- Page 13 Application Note 1507 Board Layout – 6 Layers (Continued) FIGURE 13. INNER LAYER 3 (VIEWED FROM TOP) AN1507.0 September 11, 2009...
- Page 14 Application Note 1507 Board Layout – 6 Layers (Continued) FIGURE 14. INNER LAYER 4 (VIEWED FROM TOP) AN1507.0 September 11, 2009...
- Page 15 Application Note 1507 Board Layout – 6 Layers (Continued) FIGURE 15. PCB – BOTTOM LAYER (VIEWED FROM TOP) AN1507.0 September 11, 2009...
- Page 16 Application Note 1507 Board Layout – 6 Layers (Continued) FIGURE 16. TOP ASSEMBLY DRAWING AN1507.0 September 11, 2009...
- Page 17 Application Note 1507 Board Layout – 6 Layers (Continued) FIGURE 17. BOTTOM ASSEMBLY DRAWING AN1507.0 September 11, 2009...
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Page 18: Bill Of Materials
Application Note 1507 Bill of Materials REFERENCE PART NUMBER QTY UNIT DESIGNATOR DESCRIPTION MFR NAME MFR PART H1045-00104-16V10-T C7, C42, C60, C61, CAP, SMD, 0603, 0.1µF, MURATA GRM39X7R104K016AD C63, C64, C65 16V, 10%, X7R, ROHS H1045-00105-25V10-T C8, C9, C16, C24, CAP, SMD, 0603, 1µF, MURATA GRM188R61E105KA12D... - Page 19 Application Note 1507 Bill of Materials (Continued) REFERENCE PART NUMBER QTY UNIT DESIGNATOR DESCRIPTION MFR NAME MFR PART 3-644456-4 JP1, JP2, JP3 CONN-HEADER, 1x4, AMP/TYCO 3-644456-4 VERTICAL, TIN, WHT NYLON, ROHS 881545-2 a) JP1-Pins 3 and 4, CONN-JUMPER, SHUNT TYCO 881545-2 JP2-Pins 3 and 4, LP W/HANDLE, 2P,...
- Page 20 MFR PART SN74AUP1G17DCKR IC-BUFFER, SCHMITT TEXAS SN74AUP1G17DCKR TRIGGER, 5P, SC-70-5, INSTRUMENTS 3.6V, 4mA, ROHS ZL6100ALNFT U1, U2, U3 IC-DIGITAL DC-DC INTERSIL ZL6100ALNFT CONTROLLER, 36P, QFN, 6x6, ROHS BSC016N03LSG Q3, Q4, Q7, Q8, TRANSIST-MOS, INFINEON BSC016N03LSG Q11, Q12 N-CHANNEL, 8P, TECHNOLOGY...
- Page 21 Application Note 1507 Bill of Materials (Continued) REFERENCE PART NUMBER QTY UNIT DESIGNATOR DESCRIPTION MFR NAME MFR PART H2510-03162-1/16W1-T RES, SMD, 0402, 31.6k, VENKEL CR0402-16W-3162FT 1/16W, 1%, TF, ROHS H2510-03482-1/16W1-T R11, R24, R35, R62 RES, SMD, 0402, 34.8k, PANASONIC ERJ-2RKF3482 1/16W, 1%, TF, ROHS H2510-03832-1/16W1-T RES, SMD, 0402, 38.3k,...
- Page 22 Application Note 1507 Bill of Materials (Continued) REFERENCE PART NUMBER QTY UNIT DESIGNATOR DESCRIPTION MFR NAME MFR PART J2, J4 DO NOT POPULATE OR PURCHASE JP4, JP5, JP6, JP7, DO NOT POPULATE OR PURCHASE a) TP1-TP10,TP12- DO NOT POPULATE OR TP40, TP42, TP43, PURCHASE TP46,...
- Page 23 The following text is loaded into the ZL6100 devices on the EV2 as default settings. Each PMBus command is loaded via the PowerNavigator software. The # symbol is used for a comment line. # Configuration file for ZL6100EVAL2Z-Ch1A #Erase default and user stores...
- Page 24 0x0121 # Ishare Group 1, members 2, position 1, CS En DDC_CONFIG 0x0101 # DDC Rail ID 1, Broadcast Group 1 DDC_GROUP 0x00000000 STORE_DEFAULT_ALL RESTORE_DEFAULT_ALL -------------------------------------------------------------------------------------- # Configuration file for ZL6100EVAL2Z-Ch1B #Erase default and user stores RESTORE_FACTORY STORE_DEFAULT_ALL STORE_USER_ALL RESTORE_DEFAULT_ALL MFR_ID Zilker_Labs...
- Page 25 Application Note 1507 IOUT_AVG_UC_FAULT_LIMIT -40.0 MFR_IOUT_OC_FAULT_RESPONSE 0xBF MFR_IOUT_UC_FAULT_RESPONSE 0xBF VIN_OV_FAULT_LIMIT 14.0 VIN_OV_WARN_LIMIT 13.5 VIN_OV_FAULT_RESPONSE 0x80 VIN_UV_WARN_LIMIT 4.641 VIN_UV_FAULT_LIMIT 4.50 VIN_UV_FAULT_RESPONSE 0x80 OT_FAULT_RESPONSE 0xBF UT_FAULT_RESPONSE 0xBF POWER_GOOD_ON 1.35 POWER_GOOD_DELAY 10.0 TON_DELAY TON_RISE TOFF_DELAY TOFF_FALL DEADTIME 0x3838 DEADTIME_CONFIG 0x0606 MAX_DUTY INDUCTOR 0.56 FREQUENCY_SWITCH 300 # kHz #CompZL Taps for G=36,...
- Page 26 Application Note 1507 -------------------------------------------------------------------------------------- # Configuration file for ZL6100EVAL2Z-Ch2 #Erase default and user stores RESTORE_FACTORY STORE_DEFAULT_ALL STORE_USER_ALL RESTORE_DEFAULT_ALL MFR_ID Zilker_Labs MFR_MODEL ZL6100EVAL2ZR2 MFR_REVISION Cfg Rev 1.1 MFR_LOCATION Austin_TX MFR_DATE 08_27_09 MFR_SERIAL VOUT_COMMAND 1.50 VOUT_DROOP VOUT_UV_FauLT_LIMIT 1.275 VOUT_UV_FAULT_RESPONSE 0x80 VOUT_OV_FauLT_LIMIT 1.80...
- Page 27 Application Note 1507 # Advanced USER_CONFIG 0x0030 # SYNC Output MFR_CONFIG 0x82D5 INTERLEAVE 0x0140 TEMPCO_CONFIG 0xA8 TRACK_CONFIG 0x00 # Advanced 2 MISC_CONFIG 0x0080 ISHARE_CONFIG 0x0200 # Ishare Group 2, members 1, position 1, CS disabled DDC_CONFIG 0x0202 # DDC Rail ID 2, Broadcast Group 2 DDC_GROUP 0x00000000 STORE_DEFAULT_ALL...
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Page 28: Measured Data
Application Note 1507 Measured Data The following data was acquired using a ZL6100EVAL2Z rev 3 evaluation board. Efficiency The measured input power includes the quiescent current for all three controllers on the evaluation board and is included in the efficiency measurement for the separate channels. - Page 29 Application Note 1507 Ramp-up/Ramp-down Characteristics -0.5 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 TIME (s) FIGURE 20. CHANNEL 1 RAMP UP -0.5 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 TIME (s) FIGURE 21. CHANNEL 1 RAMP DOWN AN1507.0 September 11, 2009...
- Page 30 Application Note 1507 Ramp-up/Ramp-down Characteristics (Continued) -0.5 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 TIME (s) FIGURE 22. CHANNEL 2 RAMP UP -0.5 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 TIME (s) FIGURE 23. CHANNEL 2 RAMP DOWN AN1507.0 September 11, 2009...
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Page 31: Dynamic Load Response
Application Note 1507 Dynamic Load Response 0.005 -0.005 -0.010 -0.015 -0.020 -0.025 -0.030 -0.035 -0.040 0.05 0.10 0.15 0.20 0.25 0.30 0.35 TIME (s) FIGURE 24. CHANNEL 1 DYNAMIC RESPONSE, 30A TO 42A LOAD STEP 0.030 0.025 0.020 0.015 0.010 0.005 -0.005 -0.010... - Page 32 Application Note 1507 Dynamic Load Response (Continued) 0.015 0.010 0.005 -0.005 -0.010 -0.015 -0.020 -0.025 -0.030 -0.035 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 TIME (s) FIGURE 26. CHANNEL 2 DYNAMIC RESPONSE, 21A TO 15A LOAD STEP 0.030 0.025 0.020...
- Page 33 Command Set, Intersil Corporation, 2009. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding.
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