Lsi Pin Description; Zfx-2 (Xy297A00) Dsp - Yamaha EMX 660 Service Manual

LSI PIN DESCRIPTION

ZFX-2 (XY297A00) DSP

PIN
NAME I/O
NO.
1 ED2 I/O
2 ED3 I/O
3 ED4 I/O
4 ED5 I/O
5 ED6 I/O
6 ED7 I/O
7 VSS -
8 VDD -
9 CLKM0 I
10 CLKM1 I
11 TMS I
12 TDI I
13 TCK I
14 CLKIN I
15 VSS -
16 VDD -
17 CLKO O
18 EA12/ED8 I/O
19 EA13/ED9 I/O
20 EA14/ED10 I/O
21 EA15/ED11 I/O
22 VSS -
23 VDD -
24 EA16/ED12 I/O
25 EA17/ED13 I/O
26 EA18/ED14 I/O
27 EA19/ED15 I/O
28 EA4/ED16 I/O
29 EA5/ED17 I/O
30 EA6/ED18 I/O
31 EA7/ED19 I/O
32 VSS -
33 VDD -
34 EA8/ED20 I/O
35 EA9/ED21 I/O
36 EA10/ED22 I/O
37 EA11/ED23 I/O
38 TEST0 I
39 TEST1 I
40 TEST2 I
41 TEST3 I
42 /BIO I
43 /INT1 I
44 ARBC1 I
45 ARBC2 I
46 AX1 O
47 AX2 O
48 AX3 O
49 VSS -
50 VDD -
Z: High inpedance
FUNCTION



External Memory and I/O Data Bus









Ground
Power Supply

Clock Mode


1 min. 3fold 5fold PLL BYPASS

CLKM0 0 1 0 1


CLKM1 0 0 1 1
TAP(Test Access Port) Mode Select
TAP Data Input
TAP Clock
Master Clock
Ground
Power Supply
Machine Clock Output



External SRAM and ROM Address Bus/ External DRAM and I/O Data Bus




Ground
Power Supply



External SRAM and ROM Address Bus/ External DRAM and I/O Data Bus







External Memory Address Bus/ External I/O Data Bus




Ground
Power Supply



External Memory Address Bus/ External I/O Data Bus







Test Mode Control




Separate Control Input
Interrupt 1
Audio Data Receive Unit 1 bit Clock
Audio Data Receive Unit 2 bit Clock
Audio Data Transmitt Unit 1 Data Output
Audio Data Transmitt Unit 2 Data Output
Audio Data Transmitt Unit 3 Data Output
Ground
Power Supply
PIN
NAME I/O
NO.
51 HX/SDA I/O/Z
52 /EMPTY O/Z
53 AXLR2 I
54 AR1 I
55 AR2 I
56 HRBCK/SA0 I
57 HR/SA1 I
58 HRS/SA2 I
59 VSS -
60 VDD -
61 HXBCK/SCL I
62 HXS/SA3 I
63 /CS/SA4 I
64 HBCKS/SA5 I
65 I 2 CSEL I
66 VSS -
67 VDD -
68 AXBC1 I
69 AXBC2 I
70 AXLR1 I
71 DIV8 O
72 /LAV O
73 /LMV O
74 /DRDY O/Z
75 EMU0 I/O/Z
76 EMU1 I/O/Z
77 TDO O/Z
78 DIV512 O
79 ARLR1 I
80 ARLR2 I
81 HDIR/SA6 I
82 SEL5V3V I
83 /MUTE I
84 /TRST I
85 /RS I
86 VSS -
87 VDD -
88 /IOE O
89 /RAS/SRCS O
90 /CAS/SROE O
91 /ROME O
92 /WE O
93 EA0 O
94 EA1 O
95 EA2 O
96 EA3 O
97 VSS -
98 VDD -
99 ED0 I/O
100 ED1 I/O
SUB: IC306
FUNCTION
Host Interface Data Output/I2C Bus Data
CMEM Update Buffer and HR Resistor Empty Flag Output
Audi o Data Transmi t t Uni t 2/3 Left and Ri g ht Channel Frame Frequency Si g nal
Audio Data Receive Unit 1 Data Input
Audio Data Receive Unit 2 Data Input
Host Interface Receive Clock / I2C Bus Address 0
Host Interface Data Input/ I2C Bus Address 1
Host Interface Recei v e Data Frame Frequency Si g nal / I2C Bus Address 2
Ground
Power Supply
Host Interface Transmitt Clock/ I2C Bus Clock
Host Interface Transmi t t Data Frame Frequency Si g nal / I2C Bus Address 3
Host Interface Chip Select/ I2C Bus Address 4
HRBCK/HXBCK Active Edge Select/ I2C Bus Address 5
Host Interface Mode Select
Ground
Power Supply
Audio Data Transmitt Unit 1 bit Clock
Audio Data Transmitt Unit 2/3 bit Click
Audi o Data Transmi t t Uni t 1 Left and Ri g ht Channel Frame Frequency Si g nal
Machine Clock Output then 8 min.
Ruch ALU Overflow Frag Output
Ruch MAC Overflow Frag Output
Host Interface Transmitt Data Ready Frag Output
Emurator Interrupt 0
Emurator Interrupt 1
TAP(Test Access Port) Data Output
Machine Clock then512 min.
Audi o Data Recei v e Uni t 1 Left and Ri g ht Channel Frame Frequency Si g nal
Audi o Data Recei v e Uni t 2 Left and Ri g ht Channel Frame Frequency Si g nal
Host Interface Data Format Select/ I2C Bus Address 6
Input Level Control
Mute Control
TAP(Test Access Port) Reset
Hardware Reset
Ground
Power Supply
External I/O Enable
External DRAM Low Address Strove/External SRAM Chip Select
External DRAM Cul u mn Address Strove/External SRAM Output Enabl e
External ROM Enable
External Memory and I/O Wright Enable



External Memory and I/O Address Bus





Ground
Power Supply
External Memory and I/O Data Bus
EMX660
15