Sony hcd-dz230 Service Manual page 63

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Pin No. Pin Name
48 RESERVED
49 USB_VDD3
50
51
52
53
54
55 DVDD18
56 to 64 HA2 to 8, 18, 19
65
66
67 to 75 HA16 to 9, 20
76 XROMCS
77
78
79, 80
81
82 to 86 HD2 to 6
87
88 RESERVED
89
TE
L 13942296513 90
91, 92
93 DVDD18
94 RESERVED
95 RESERVED
96
97
98
99
100
101
102
103 HDMI_SCL
104 HDMI_SDA
105
106
107
108 xSYSRST
109 RESERVED
110
111
112
www
113 to 117
118
119 to 129 RD2 to 0, 15 to 8
.
130 LIMITSW
131
132
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I/O
— USB port DMINUS pin for HS DL (not used (Open))
— Power supply (SW+3.3V)
SPFG I Spindle FG input
MSW O DVD/CD switch (H:DVD / L:CD)
CKSW I CKSW input
OCSW I OCSW input
EEWP O EEPROM Write Protect control (L:Write allowed)
— Power supply (+1.8V from IC1110)
O Host address bus 2 to 8, 18, 19 output to Flash ROM (IC1102)
DVDD3 — Power supply (SW+3.3V)
XWR O Write enable output to Flash ROM (IC1102) (active Low)
O Host address bus 15 to 9, 20 output to Flash ROM (IC1102)
O Chip select output to Flash ROM (IC1102) (active Low)
HA1 O Host address bus 1 output to Flash ROM (IC1102)
XRD O Read enable output to Flash ROM (IC1102) (active Low)
HD0,1 I/O Host data bus 0,1 input/output for Flash ROM (IC1102)
DVSS — Ground terminal
I/O Host data bus 2 to 6 input/output for Flash ROM (IC1102)
HA21 O Host address bus 21 output to Flash ROM (IC1102)
— Not used (Open)
HD7 I/O Host data bus 7 input/output for Flash ROM (IC1102)
DVSS — Ground terminal
HA17, 0 O Host address bus 17, 0 output to Flash ROM (IC1102)
— Power supply (+1.8V from IC1110)
— Not used (Open)
— Not used (Open)
DVDD3 — Power supply (SW+3.3V)
IFSDO O Ext. CPU Serial data output (H/W method)
IFCK O Ext. CPU Serial clock (H/W method)
xIFCS O Chip select for Ext.CPU (Low Active, H/W method)
IFSDI I Ext. CPU Serial data input (H/W method)
SCL O IIC clock output to E2PROM and HDMI controller
SDA I/O IIC data input/output for E2PROM and HDMI controller
O HDMI DDC line SCL
I/O HDMI DDC line SDA
RXD I RS232C RXD signal input from Jig
TXD O RS232C TXD signal output to Jig
ICE O ICE mode enable (not used (Open))
I Reset input from system controller (IC501) (active Low)
I IR control signal input (not used (Open))
xTXINT I Interrupt signal from HDMI controller (not used (Fixed "H" (SW+3.3V)))
DQM0 O Lower byte mask output to SDRAM (IC1104) (H:Mask / L:Enable)
IFBSY I Ready/Busy interrupt signal input from system controller (IC501) (H:Busy / L:Ready)
RD7 to 3 I/O Data bus 7 to 3 input/output for SDRAM (IC1104)
x ao
DVDD3 — Power supply (SW+3.3V)
y
I/O Data bus 2 to 0, 15 to 8 input/output for SDRAM (IC1104)
i
I LIMITSW signal input
DVDD3 — Power supply (SW+3.3V)
DQM1 O Upper byte mask output to SDRAM (IC1104) (H:Mask / L:Enable)
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HCD-DZ230/DZ231/HDZ235
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Description
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