System Control/Signal Processor Block Diagram - Sony DVP-NS50P Service Manual

3-3. SYSTEM CONTROL/SIGNAL PROCESSOR BLOCK DIAGRAM

MV-045 BOARD
(SEE PAGE 4-7 to 4-8)
IC103
EEPROM
IC104
64M SDRAM
146,147,149~151,158~160 115,117,118,120,121,123~126,128~133,135
SCL 6 102 SCL
SDA 5 103 SDA
228 229
9 IC101
228
X102
3.3Vp-p
27MHz
8 IC101 203 7 IC101
202
0.7Vp-p
H
H
3-5
IC102
16M ROM
138 139 140 142 156 157 143 145 113 137 53~61,67~72,74~76,78,89,92,93 81~84,86~88,91
IC101
CXD9849R
MICROPROCESSOR
AVDECODER
SERVO DSP
209 203 202 200 198 194 196
6 IC101 C/BAR PB 5 IC101 C/BAR PB 4 IC101 C/BAR PB
200 198 199
0.7Vp-p
1Vp-p 1Vp-p
1Vp-p
H H H
IOOE 79
IOWR 66
IOCS 77
IC101
10 156
3.3Vp-p
110MHz
RESET IC
IC 108
1
CN 106
IFBSY 105
IFSCK 99
IFSDO 98
XIFCS 100
IFSDI 101
PRST 110
A_MUTE
TO MV-045
AUDIO
ABCK 214 ABCK (SEE PAGE 3-10)
ALRCK 213 ALRCK
ACLK
ACLK 215
SPDIF 225 SPDIF
TO MV-045
AUDIO
XRST 220 XRST
(SEE PAGE 3-9)
MAMUTE 176 MAMUTE
ASDATA4 222 ASDATA4
11 IC101 215
3.3Vp-p
24MHz
V MUTE
C
Y
TO MV-045
V
VIDEO
Y/G
(SEE PAGE 3-11)
CB/B
CR/R
WIDE
3 IC101 C/BAR PB
196
286 mVp-p (NTSC)
300 mVp-p (PAL)
H
3-6
DVP-NS50P/NS41P/NS52P
5 IFBSY
9 IFSCK
7 IFSDO
TO IF 124
XIFCS
4
INTERFACE
6 IFSDI
(SEE PAGE 3-14)
XSYSRST
2
10 V MUTE
14 A MUTE