Sharp XV-C1E Service Manual page 30

XV-Cl E
No. Pin name I/O
43 DGND
44 DY 0
4 5 CLY 0
4 6 C L Y
0
4 7 ENOUT 0
48
49 DGND
50 TEST6 I
51 OE I
52 NAOUT 0
5 3 NAIN2 I
5 4 NAlNl
55 0
5 6 F R P 0
57 CSYNC I
58 MVSYNC 0
5 9 V L S 0
6 0 lNVlN2 I
61 0
6 2 M F S 0
6 3 V C C
6 4 G N D
The GND and DGND pins are interconnected inside the chip with a resistor in between. Be sure to keep
l
both pins at the same potential.
When the OE input level gets low, all the output signals to the TFT panel - DX, CLXi, CLXi (i =l thru 4),
l
Be sure to fix the non-used inverter input and NAND input at the high or low level.
l
Switching between the VIDEO and WIDE modes goes as follows depending on the WMODE and
l
VMODE input levels. L: Low level, H: High level.
WMODE VMODE
In the power-saving mode with no display, the CLXl thru CLX4 signals are all at low level, whereas the
l
Keep all the test terminal inputs at low level.
l
Keep open the test terminal reference signal outputs - MOUTl and MOUT2.
l
Connection
Power.
Output to TFT panel. TFT panel' s Y-direction shift data output (VDD2 line).
Output to TFT panel.
Output to TFT panel.
Output to TFT panel.
Power.
Power.
Output to video circuit.
Display mode
Intermittent PAL
Letter box (NTSC)
Function
High-voltage power ground (OV).
TFT panel' s Y-direction transfer clock output (VDD2 line).
TFT panel' s Y-direction transfer clock output (VDD2 line).
TFT panel' s enable signal output (VDD2 line).
High-voltage power 2 (+12.OV typical).
High-voltage ground (OV).
Test terminal input.
Output enable control input.
NAND output.
NAND input 2.
NAND input 1.
1 H inverted signal output (output to chroma IC).
Composite sync signal input.
Vertical sync signal monitor output.
Video level setting signal output for WIDE mode.
lnverter input 2.
lnverter output 2..
Field ID signal monitor output.
Logic circuit power (+5V typical).
Logic circuit power ground (OV).
VLS: During the " H" period, the black-level video
signal is put into the TFT panel.
30
Remarks