Pin Assignment - Denon DN-D9000 Service Manual

128M SDRAM
(DS: IC302, 303, 402, 403)
1
TOP VIEW
27
uPC1934GR-1JG-E1 (RC: IC310)
TOP VIEW
C 1 16
T
R 2 15
T
I 3 14
N1
I 4 13
I1
FB 5 12
1
DTC 6 11
1
OUT 7 10
1
GND 8 9
4M FLASH MEMORY (M29W800AB)
(DS: IC502, 509)
1 48
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
W
TOP
RP 12 37
NC 13 VIEW 36
NC
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
24 25

Pin Assignment

Pin No. Pin Name
54
22, 23~26, A0~A11 Address
29~35
20, 21 BS0, Bank Select
BS1
2, 4, 5, 7, 8, DQ0~ Data Input/Output
10,11, 13, 42, DQ15
44,45, 47, 48,
50, 51, 53
19 CS# Chip Select
18 RAS# Row Address Strobe
17 CAS# Column Address Strobe Referred to RAS#
16 WE# Write Enable
15, 39 UDQM/ input/output mask
LDQM
38 CLK Clock Inputs
37 CKE Clock Enable
28
1, 14, 27 Vcc Power (+3.3V)
28, 41, 54 Vss Ground
3, 9, 43, 49 VccQ Power (+3.3V) for I/O buffer Separated power from Vcc, used for output buffers to improve noise.
6, 12, 46, 52 VssQ Ground for I/O buffer
36, 40 NC No Connection
V
REF
16
V
REF
Ref. V
DLY
Circuit
I
N2
I
I2
FB
2
DTC
2
Oscillator
OUT
2
V
CC
1
C
T
W29EE011P (FG: IC507)
A16
BYTE
V
SS
4
DQ15A-1
A7
DQ7 5
DQ14 A6
6
DQ6
A5 7
DQ13
A4
8
DQ5
A3 9
DQ12
A2 10
DQ4
A1 11
V
CC
A0 12
DQ11
DQ0 13
DQ3
14 15 16 17 18 19 20
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V
SS
E
A0
Function
Multiplexed pins for row and column address.
Row address: A0~A11. Column address: A0~A8.
Select bank to activate during row address latch time, or bank to
read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When command decoder is
disabled, new command is ignored and previous operation continues.
Command input. When sampled at the rising edge of the clock,
RAS#, CAS# and WE# define the operation to be executed.
Referred to RAS#
The output buffer is placed at Hi-A (with latency of 2) when DQM is
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
System clock used to sample inputs on the rising edge of clock.
CKE controls the clock activation and deactivation. When CKE is low,
Power Down mode, Suspend mode, or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Separated ground from Vss, used for output buffers to improve noise.
No Connection
DLY I I
N2 I2
15 14 13
Timer Latch
Type Protection
+
E/A
2
MOS Input
MOS Output
+
E/A
1
2 3 4 5
R I I FB
T N1 I1 1
V
DD
V
SS
CE
OE
WE
3 2 1 32 31 30
29 A14
A0
.
28 A13
.
.
27 A8
.
.
26 A9 .
TOP
.
25 A11
A16
VIEW
24
OE
A10
23
22
CE
Terminal Function
21 DQ7
DN-D9000
Description
FB DTC OUT V
2 2 2 CC
12 11 10 9
MOS Output
+
PWM
2
MOS Output
+
PWM
1
6 7 8
DTC OUT GND
1 1
DQ0
OUTPUT
CONTROL
BUFFER
DQ7
CORE
DECODER
ARRAY
Name Function
A0 - A16
Address Inputs
DQ0 - DQ7 Data Inputs/Outputs
CE Chip Enable
OE Output Enable
Write Enable
WE
Power Supply
VDD
Ground
GND
NC No Connection
:
29