Dvr-S120 Block Diagram - Yamaha DVX-S120 Service Manual

A
Q Q
3 7 6 3 1 5 1 5 0
DVR-S120 BLOCK DIAGRAM / ブロックダイアグラム
1
LOADER
A97ST
2
3
T E
L 1 3 9 4 2 2 9 6 5 1 3
SDRAM
512K x 32 x 4
1M x 32 x 4
4 MDQM [0:3 ]
MT48LC4M32B2TG-7
MT48LC2M32B2TG-7-TR
Module interface bus
5
w w w
.
6
B C
ATAPI
Connector
UPA [1:3 ]
UPD [0:15 ]
DTACKn
LDS
UDS
HDMAC K
HDMARQ
LDRST
IDECS [0:1 ]
HCSn [3:4 ]
HIRQ1
A TAPI
MA [0:11 ]
BA [0:1 ] SDRAM interface
MD [0:31 ]
MCS0n
MRASn
MCASn MCS1n
MWEn
MCLK
GPIO I2C
(misc ) Master
GPIO SCL
IR SD A
SCL
SD A
x a o
y
NVRAM
64K bits
i
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8
DVD (MPEG) BOARD
A TAPI connector
Flash
HRST 1 2 GND
HD (15 ) 3 4 H D (0 )
1M x 16
HD (14 ) 5 6 H D (1 )
2M x 16
HD (13 ) 7 8 H D (2 )
TSOP48
HD (12 ) 9 1 0 H D (3 )
HD (11 ) 11 12 HD (4 )
HD (10 ) 13 14 HD (5 )
HD (9 ) 15 16 HD (6 ) UPA [1:22 ]
HD (8 ) 17 18 HD (7 ) UPD [0:15 ]
GND 19 20 SYSRSTn
DMARQ 21 22 GND UDS
LDS 23 24 GND
FLASHCSn
UDS 25 26 GND
DTACKn 27 28
DMACK 29 30 GND
HIRQ1 31 32
Trans p arent latch
UPA2 33 34 74HCT573
UPA1 35 36 UPA3
74HCT573
IDECS0 37 38 IDECS1 74HCT573
39 40 GND
UPA [1:3 ]
UPD [0:15 ]
A LE
Q Q
3 7 6 3
Host interface
DECODER IC
LSI Logic
Ziva5
I2C A nalo g Di g ital
Slave video audio
SCL VDAC [0:4 ] SPDIF
SD A
u 1 6 3
.
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F
2 4
9 9 8
GND
MEDUSACSn
M29W160
A LE
M29W320
UPA2
ELINK
UPD15
UPD13
Connector
UPD11
UPD9
UPD8
UPD6
UPD4
UPD2
UPA [1:3 ] UPD0
UPD [0:15 ] MEDUSAINTn
A LE LDS
LDS R/W
UDS
SYSRSTn
DTACKn
MEDUSAINTn
MEDUSACSn
R/W
1 5 1 5 0 8 9 2 4
A udio I2S Service and JTAG bus
X CLK dia g nostic p ort RST
BCLK RTS1 TDO
LRCLK RXD1 TDI
A DATA0 TXD1 TMS
CTS1 TCK
Audio DAC
m
AK4382
c o
Analog Audio output
G H
DVR-S120/NX-P120
2
9 9
ELINK connector
1 2 +5V
3 4 +5V
5 6 SYSRSTn
7 8 UPA3
9 10 UPA1
11 12 UPD14
13 14 UPD12
15 16 UPD10
17 18 GND
19 20 UPD7
21 22 UPD5
23 24 UPD3
25 26 UPD1
27 28 DTACKn
29 30 UDS
31 32 GND
9 8 2 9 9
Clock
Circuit
Reset
SYSRSTn
Circuit
57