Sony DPP-MS300E Service Manual page 62

• DK-40 BOARD IC505 HG51BS263AFB (HEAD CONTROLLER, MECHANISM CONTROLLER)
Pin No. Pin Name
1 FKEY0
2 FEEDER
3 FPS
4 BUSY
5 HPS0
6 HPS1
7 IVO2
8 IVO1
9 IVI2
10 IVI1
11 IVEN
12 GND
13 XIN
14 XOUT
VCC
15
AC T
16
AC W
17
CALC
18
DRVX
19
PDT3
20
21 PDT2
PDT1
22
PDT0
23
LATX
24
25 HDCK
26 TMGE
27 DRQX
28 CKO
29 VCC
30 GND
31 CK
32 DTRX
33 TMG
34 PSTX
35 RESX
36 RDX
37 WEX
38 VCC
39 CS1X
40 CUTEX
41 REGX
42 to 51 AD10 to AD1
52 VCC
53 GND
54 to 61 DT15 to DT8
I/O
I
Sheets bit (0) input from the auto feeder unit
I
Auto feeder unit desorption detect input terminal "L": attach, "H": removed
I Auto feeder unit position detect sensor input terminal
Busy signal in/out terminal Connected to TMGE (pin @§)
I/O
I
Head position (0) detect sensor (PH1852) input terminal
I
Head position (1) detect sensor (PH1851) input terminal
O Not used (open)
O
Not used (open)
I
Not used (fixed at "L")
I
Not used (fixed at "L")
I
Not used (fixed at "L")
—
Ground terminal
I
System clock input terminal (20 MHz)
O System clock output terminal (20 MHz)
—
Power supply terminal (+5V)
I
Not used (fixed at "H")
I
Not used (fixed at "H")
O
Not used (open)
O
Strobe signal output to the thermal-head (HEAD901) "L": power on
O
Printing data (3) output to the thermal-head (HEAD901)
O Printing data (2) output to the thermal-head (HEAD901)
O
Printing data (1) output to the thermal-head (HEAD901)
O
Printing data (0) output to the thermal-head (HEAD901)
O
Serial data latch pulse output to the thermal-head (HEAD901)
O Serial data transfer clock signal output to the thermal-head (HEAD901)
Timing pulse in/out terminal Connected to BUSY (pin 4)
I/O
O
Not used (open)
O
Clock signal output terminal (20 MHz)
—
Power supply terminal (+5V)
—
Ground terminal
Clock signal input terminal (20 MHz) Connected to CKO (pin @•)
I
I Not used (fixed at "L")
Timing pulse input terminal Connected to TMG (pin (¢)
I
Print start signal input terminal Connected to PSTX (pin (∞)
I
System reset signal input from the reset signal generator (IC501) "L": reset
I
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
I
Data read enable signal input from the system controller (IC503) "L" active
I Data write enable signal input from the system controller (IC503) "L" active
—
Power supply terminal (+5V)
I
Chip select signal input from the A/D, D/A converter (IC407) "L" active
I
Address signal input for the chip select signal generate Connected to address bus (A12)
I Address signal input for the chip select signal generate Connected to address bus (A11)
I
Address signal input from the system controller (IC503)
—
Power supply terminal (+5V)
—
Ground terminal
Two-way data bus with the A/D, D/A converter (IC407), system controller (IC503) and
I/O
D-RAM (IC509) (upper 8 bit)
Description
5-65