Sony TA-E9000ES Service Manual page 70

Pin No. Pin Name
41 NC
42 DAOR
43 DAOL
44 TEST3
45 DEMP
46 FS1
47 FS2
48 to 50 TB3 to TB1
51 DATAI
52 LRCKI
53 BCKI
54 FIMCK
55 FIMO
56 GND
57 TEST2
58 TEST1
59 FIS
60 MI0
61 MI1
62 DI0
63 DI1
64 TB0
I/O
— Not used
O Rch D/A 8Fso, 4Fso data output (Not used)
O Lch D/A 8Fso, 4Fso data output (Not used)
I Test pin (Fixed at "L")
I Deemphasis setting input "L":OFF (Fixed at "L")
I
Deemphasis setting input Fsi frequency selection input (Fixed at "L")
I
I/O Test bus input/output (Open)
I Data input
I Input data 1Fs word clock input (Schmidt)
I Input data bit clock input
I Input data line Fs reference input and master clock input
O Master clock output
— Ground
I Test pin (Fixed at "L")
I The second reset signal input from system controller
FIMCK frequency division rate setting input "L":1/1 (256 Fs), "H":1/2 (512 Fs)
I
(Fixed at "H")
I Input data format setting input (Fixed at "H")
I Input data format setting input (Fixed at "L")
I
Data input (Not used)
I
I/O Test bus input/output (Open)
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Function