TIMER1
A01~A05
Address
*EXIOCS
decoder
*IOWRL
*IOWRH
*IORD
Division
CLK
circuit
D00~D15
IN00~IN04
HDALM00~06
SPALMS
SPALML
LFALMS
LFALML
Figure 5.21 MBCU20050 block diagram
Print head
driver and
controller
PD01~24
Flyback
FLYBK01~06
controller
I/O port
OUT00~07
Alarm
detection
*POWST
circuit
*DVALM