Sony CDP-XA555ES Service Manual page 43

Pin No. Pin Name
44 WDCK
45 LRCK
46 DATA
47 BCLK
48 64 DATA
49 64 BCLK
50 64 LRCK
51 GTOP
52 XUGF
53 XPLCK
54 GFS
55 RFCK
56 C2PO
57 XRAOF
58 MNT3
59 MNT2
60 MNT1
61 MNT0
62 XTAI
63 XTAO
64 XTSL
65 DVSS
66 FSTI
67 FSTO
68 C4M
69 C16M
70 MD2
71 DOUT
72 EMPH
73 WFCK
74 SCOR
I/O
O Word clock signal (88.2 kHz) output terminal Not used (open)
O L/R sampling clock signal (44.1 kHz) output to the CXD8762Q (IC600)
"L": 48-bit slot serial data output when PSSL "H": DA16 output when PSSL
O
(PSSL (pin rd) : fixed at "L") Serial data output to the CXD8762Q (IC600)
"L": 48-bit slot bit clock signal output when PSSL "H": DA15 output when PSSL
O
(PSSL (pin rd) : fixed at "L") Bit clock signal (2.8224 MHz) output to the CXD8762Q (IC600)
"L": 64-bit slot serial data output when PSSL "H": DA14 output when PSSL
O
(PSSL (pin rd) : fixed at "L")
"L": 64-bit slot bit clock signal output when PSSL "H": DA13 output when PSSL
O
(PSSL (pin rd) : fixed at "L")
"L": 64-bit slot L/R sampling clock signal output when PSSL "H": DA12 output when PSSL
O
(PSSL (pin rd) : fixed at "L")
"L": GTOP signal output when PSSL "H": DA11 output when PSSL
O
(PSSL (pin rd) : fixed at "L")
"L": XUGF signal output when PSSL "H": DA10 output when PSSL
O
(PSSL (pin rd) : fixed at "L")
"L": XPLCK signal output when PSSL "H": DA09 output when PSSL
O
(PSSL (pin rd) : fixed at "L")
"L": GFS (guard frame sync) signal output when PSSL "H": DA08 output when PSSL
O
(PSSL (pin rd) : fixed at "L")
"L": RFCK (read frame clock) signal output when PSSL "H": DA07 output when PSSL
O
(PSSL (pin rd) : fixed at "L")
"L": C2PO signal output when PSSL "H": DA06 output when PSSL
O
(PSSL (pin rd) : fixed at "L")
"L": XRAOF (RAM over flow) signal output when PSSL "H": DA05 output when PSSL
O
(PSSL (pin rd) : fixed at "L")
"L": MNT3 (monitor 3) signal output when PSSL "H": DA04 output when PSSL
O
(PSSL (pin rd) : fixed at "L")
"L": MNT2 (monitor 2) signal output when PSSL "H": DA03 output when PSSL
O
(PSSL (pin rd) : fixed at "L")
"L": MNT1 (monitor 1) signal output when PSSL "H": DA02 output when PSSL
O
(PSSL (pin rd) : fixed at "L")
"L": MNT0 (monitor 0) signal output when PSSL "H": DA01 output when PSSL
O
(PSSL (pin rd) : fixed at "L")
I System clock input terminal (16 MHz)
O System clock output terminal (16 MHz) Not used (open)
I System clock selection input terminal (fixed at "L")
— Ground terminal (digital system)
I 2/3 divider input terminal of pins ys (XATI) and yd (XTAO)
O 2/3 divider output terminal of pins ys (XATI) and yd (XTAO)
O 4.2336 MHz clock signal output terminal Not used (open)
O 16.9344 MHz clock signal output terminal Not used (open)
I Digital out on/off control signal input from the system controller (IC201)
O Digital signal (for coaxial out and optical out) output terminal
O Emphasis control signal output terminal Not used (open)
O Write frame clock signal output terminal Not used (open)
O Sub-code sync (S0+S1) detection signal output to the system controller (IC201)
Description
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
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