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DV-L70U
9-23. IC3201 MB8346BV
Pin No.
I/O
17
I
Data input terminal
14
O
Data output terminal
16
I
Shift clock input terminal
15
I
Load signal input terminal When "H" level is input, the data of the 12-bit shift register is loaded to the decoder
18,
O
D/A output teminal
19,
2,
3,
4,
5,
6,
7,
8,
9,
12,
13
11
–
Power terminal
20
–
GND terminal
10
–
Power terminal
1
–
GND terminal
• Block Diagram
DI
CLK
Terminal name
The 12-bit serial data is input.
The bit data of MSB of 12-bit shift register is output.
The input signal form the DI terminal is input into 12-bit shift register when the shift
clock reises.
and register for D/A output.
Analog data of 8-bit D/A converter with OP amplifier is output.
Power terminal of MCU interface/OP amplifier
Ground terminal of MCU interface/OP amplifier
Power terminal of D/A converter
Ground terminal of D/A converter
Vcc
D0
D1
D2
8
12
DO
DI
8 bits latch
8 bits
R-2R
D/A Converter
+
-
Vcc
GND
AO
1
12 bits shift register
D3
D4
D5
D6 D7
D8
Address decoder
1 2 3 4
12
9-29
Remarks
GND
D9 D10 D11
12
DO
DI
8 bits latch
8 bits
R-2R
D/A Converter
+
-
AO
V
Vss
12
DD
DO
LD
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