Figure 5.23Pch-Io Configuration - Advantech ARK-2151V User Manual

5.2.3.2 PCH-IO Configuration
 PCI Express Clock Gating
This item allows users to enable or disable PCI Express Clock Gating for each
root port.
 PCI Express Configuration
This item allows users to configuration PCIE1~PCIE8 root port detail settings.
 USB Configuration
This item allows users to configuration detail of USB functions.
 PCH Azalia Configuration
This item allows users to configuration detail of azalia functions.
 LAN 1/2 controller
Enables or disables the LAN 1/2 controller.
 Wake on LAN
Enables or disables LAN1 wake up from sleep state.
 LAN 1/2 PXE Rom
This item allows users to enable or disable PXE Rom for LAN 1/2.
 PCIE Wake from S5
Enables or disables PCIE device wake up from S5.
 USB Wake From S4 Support
Enable or disable USB to wake the system from S4.
 SLP_S4 Assertion Width
This item allows users to set a delay of sorts.
 Restore AC Power Loss
This item allows users to select off, on and last state.
ARK-2151V User Manual
Figure 5.23 PCH-IO Configuration
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