Parallel Interface Board - ZiLOG ZDS-1 Series User Manual

Hardware Expansion Options
Zil0g Offers
a variety of hardware expansion features t o tailor ZDS-1 Series Development Systems t o best
suit the users' microprocessor development needs. A standard bus interface structure allows the use of modu-
lar boards, each packaged with very high density LSI components for maximum reliability and performance.
In addition, software is provided with standard interface t o enable immediate use the interface.
PARALLEL INTERFACE BOARD
The PIB provides a basic parallel interface between the
ZDS-1 Series Development System and external devices pro-
vided by the user. Two Z80-PI0 components are provided
with supporting logic to give the user 32 bidirectional 110
bits. The card also contains plated through holes for insertion
of a Z80-CTC to provide four counter-timer channels. The
uncommitted PIO's and/or user supplied CTC can be inter-
faced with the system's daisy-chain priority interrupt struc-
ture. Unused space is provided with 16-pin dip locations
(Vcc on pin 16, and GND on pin 8) to allow the addition of
logic at the user's discretion. A four-bit dip switch enables
I/O port address selection while additional control logic dir-
ects port transaction with the system bus.
The flexability of the PIB is demonstrated by Ziog in
using it to design our own family of interface boards;
ASPIO, CIB and RXB.