Register 45: Ethernet Mac Target Time Seconds (Emactargsec), Offset 0X71C - Texas Instruments TM4C1294NCPDT Datasheet

Ethernet Controller
Register 45: Ethernet MAC Target Time Seconds (EMACTARGSEC), offset
0x71C
The MAC Target Time Seconds (EMACTARGSEC) register, along with the MAC Target Time
Nanoseconds (EMACTARGNANO) register, is used to schedule an interrupt event.
Ethernet MAC Target Time Seconds (EMACTARGSEC)
Base 0x400E.C000
Offset 0x71C
Type RW, reset 0x0000.0000
31 30 29
Type RW RW RW
Reset 0 0 0
15 14 13
Type RW RW RW
Reset 0 0 0
Bit/Field Name
31:0 TSTR
1544
28 27 26 25
RW RW RW RW
0 0 0 0
12 11 10 9
RW RW RW RW
0 0 0 0
Type Reset
RW 0x0
Texas Instruments-Production Data
24 23 22 21
TSTR
RW RW RW RW
0 0 0 0
8 7 6 5
TSTR
RW RW RW RW
0 0 0 0
Description
Target Time Seconds Register
This register stores the time in seconds. When the timestamp value
matches or exceeds both the MAC Target Time Seconds
(EMACTARGSEC) and MAC Target Time Nanoseconds
(EMACTARGNANO) registers, then based on the TRGMODS0 bit field
in the MAC PPS Control (EMACPPSCTRL), the MAC starts or stops
the PPS signal output and generates an interrupt (if enabled).
20 19 18 17
RW RW RW RW
0 0 0 0
4 3 2 1
RW RW RW RW
0 0 0 0
June 18, 2014
16
RW
0
0
RW
0