JVC LT-26DB1BU/AX Service Manual page 37

Integrated digital terrestrial/satellite lcd television
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MAIN PWB CIRCUIT DIAGRAM (6/28) [Douglas_USB,I2C,JTAG]
5
UART0 : PC Display Debug message
UART1 : G-Probe application run at PC & Serial command
I2C0 : FLI_SDA1 , FLI_SCL1 (Micom,eeprom,HDMI switch, Audio Amp)
I2C1 : FLI_SDA0 , FLI_SCL0 (Demode IC , LNB IC)
D
+3V3_A
R113
222/1005
R115
222/1005
R116
222/1005
R117
222/1005
FLI_SDA0
MAIN PWB
FLI_SDA0
FLI_SCL0
(26/28),(27/28),(28/28)
FLI_SCL0
FLI_SDA1
MAIN PWB
FLI_SDA1
FLI_SCL1
FLI_SCL1
(5/28),(16/28),(22/28)
UART0_RX
UART0_TX
UART1_RX
UART1_RX
MAIN PWB (23/28)
UART1_TX
UART1_TX
MAIN PWB (13/28)
P_DIM
A_DIM
MAIN PWB (9/28)
CI_PWR
MAIN PWB (5/28)
FLI_INT
C
+3V3_A
L111
C117
BLM18PG300SN1D
104p/16V/1005
R128
622/F/1005
C118
47uF/16V/MVK/S
B
C125
5R0p/50V/1005
R134
OPEN-153/1005
R133
OPEN-153/1005
+5V
R138
103/1005
A
R137
103/1005
All location are from 111 to 160
5
4
U112G
&MPEG2_ONECHIP FLI10610H
OTP_VDD33
R120
330/1005
D21
2WIRE_M1_SDA_UART2_TX
R118
330/1005
D20
2WIRE_M1_SCL_UART2_RX
RESET_N
R119
330/1005
F20
2WIRE_M0_SDA
R121
330/1005
E20
2WIRE_M0_SCL
REF_CLK
A19
UART0_RXD
XTAL_IN
B19
UART0_TXD
CLKOUT
A20
UART1_RXD
B20
UART1_TXD
OBUFC_CLK
TP116
1
C20
UART1_RTS
PCB_TP08
1
C19
UART1_CTS
TP113
PCB_TP08
A13
PWM3
B13
PWM2_GPIO6
C13
PWM1_GPIO5_/INT5
D13
PWM0_GPIO4_/INT4
C29
USB_FLAG
EJ_RST_N
C28
USB_PWREN
EJ_DINT
USB_D0+
AJ20
USBPHY_PADP
USB_D0-
AH20
USBPHY_PADM
DFSYNC_IN_OUT_GPIO8
AG20
USBPHY_VRES
C120
AG19
USB_AVDD33
104p/16V/1005
AH19
USB_AVDD33
AF20
USB_AVDD33
TESTMODE0
TESTMODE1
AF19
USB_GND
USB_AVDD12
AJ19
USB_GND
AD20
USB_GND
C119
C121
105p/16V/1005
104p/16V/1005
JP112
+5V_USB
KJA-UB-4-0004
L113
ACM2012H-900
1
VBUS
SGND
1
1
2
2
D-
2
3
D+
3
4
3
4
GND
SGND
4
RV111
C126
OPEN-AVRL161A1R1NTB
5R0p/50V/1005
RV112
OPEN-AVRL161A1R1NTB
+5V
C127
106p/16V/2012
R139
000/1005
L114
1
5
EN
OUT
BLM21PG600SN1D
4
IN
3
2
FLG
GND
U104
C128
R5523N USB HIGH-SIDE POWER SWITCH
104p/16V/1005
4
(No.YA698<Rev.001>)2-17
3
+3V3_A
U111
R111
OPEN-ASM811REUSF-T
OPEN-104/1005
1
GND
2
RESET
Reset Threshole
C112
: +3.08V
TP112
OPEN-680p/1005
R114
R112
PCB_TP08
OPEN-104/1005
A26
1
D23
MAIN PWB (8/28)
PWR_/RESET
Y111
R122
000/1005
19.6608MHZ/
A22
1
2
20PF/SX-1/SMD
A23
TP111
E12
1
R124
OPEN-000
PCB_TP08
NVRAM_WP
F21
C113
C114
270p/50V/1005
270p/50V/1005
TRST#
B26
TRST
B27
TDI
TDI
TDO
A27
TDO
TMS
A28
TMS
TCK
B28
TCK
EJTAG_RST#
A29
DINT
B29
E13
BLT_EN
MAIN PWB (13/28)
TP114 PCB_TP08
C27
1
C26
1
TP115 PCB_TP08
+1V2
L112
AE20
BLM18PG300SN1D
C123
C124
104p/16V/1005
106p/10V/2012
5
6
+5V_USB
MAIN PWB ASS'Y (6/28)
C129
[Douglas_USB,I2C,JTAG]
100uF/25V/BXE/S
HU-71100005
3
2-18(No.YA698<Rev.001>)
2
+3V3_A
4
VCC
3
LPM_RST_N
MR
1
2
000/1005
S111
OPEN-JTP1127WEM
3
4
+3V3_A
R123
102/1005
PR111
103*4/1005
1
8
2
7
3
6
4
5
+3V3_A
JP111
OPEN-2110-DS14-G
1
3
R125
200/1005
5
7
9
11
13
R126
102/1005
R127
103/1005
C115
200p/50V/1005
EJTAG
EEPROM
Address:0xA4/A5
+3V3_A
C122
104p/16V/1005
U113
24LC256
1
8
A0
VCC
WP
2
7
A1
WP
3
6
FLI_SCL1
A2
SCL
FLI_SDA1
4
5
VSS
SDA
UART0 : Message
OPEN
OPEN-53014-0410
2
1
MAIN PWB (5/28)
D
2
4
6
8
C
10
+3V3_A
12
14
C116
104p/16V/1005
+3V3_A
R131
103/1005
R132
103/1005
Q111
NVRAM_WP
1
MMBT4401
NVRAM_WP : H = Enable write
NVRAM_WP : L = Disable write
B
+5V
R135
R136
JP113
472/1005
472/1005
1
UART0_TX
2
UART0_RX
3
4
A
1
lt-26_32db1bu_0514_4/30_0.0

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