Sony dvp-s3000 Service Manual page 35

(5-12) IC216 (CXD1186) register check
Register write n Register read collating check
Registers to be checked: DADRC_L (0x06380007)
DADRC_H (0x06380008)
HXFRC_L (0x06380009)
HXFRC_H (0x0638000A)
HADRC_L (0x0638000B)
HADRC_H (0x0638000C)
Incrementing 1 each starting from 0, data are written to readable
and writable registers, then they are read for checking. Incrementing
initial value by 1 each, a check is repeated 256 times.
If compared data are not same, a checking is suspended, and error
code 05, its address, written data, and read data are displayed.
(5-13) IC216 (CXD1186) SRAM check
IC093 (Syscon ROM) n IC216 (CXD1186) n IC215 (SRAM)
n IC216 read collating check
Checking range: 0x00000000 - 0x00007fff
IC093 ROM pattern is copied to all areas to be checked. Each time
256 bytes are copied, 255 bytes of original (ROM) address are re-
turned. A reading check is made after data are written to all areas.
After SRAM write addresses are set, error code 03 when writing is
not ready, or after read addresses are set, error code 04 when read-
ing is not ready is output, then a check is finished.
Also, if compared data are not same, a check is suspended, and
error code 05, its address, written data, and read data are displayed.
(5-14) IC216 (CXD1186) to IC217 (CXD8598R) connection check
IC093 (ROM) n IC216 (CXD1186) n IC217 (CXD8598R)
VCD bit stream data stored in IC093 are transferred to the IC215
(external SRAM of IC216), and IC217 (CXD8598R) transfer end
interruption is checked, which occurs by flowing data to the IC217
(CXD8598R).
If the transfer end interruption is not detected, the error code 21 is
output.
Further, SCR is read to check its value. If the value is not the one in
sector transferred, the error code 22 is output.
(6) Video Decoder
(6-2) IC281 (CXD1900BQ) reset check
Write to register n Hard reset n Read from register
Register to be checked: PLYMOD (0x06080002)
Data other than 0 are written to readable and writable register in
IC281 (CXD1900BQ), and they are read after hard reset, then the
error code 02 is output if they are not cleared to 0.
(6-3) IC281 (CXD1900BQ) register check
Register write n Register read collating check
Register to be checked: PLYMOD (0x06080002)
Incrementing 1 each starting from 0, data are written to readable
and writable register, then they are read for checking. Incrementing
initial value by 1 each, a check is repeated 256 times. However,
some bits that cannot be written are masked.
If compared data are not same, a checking is suspended, and error
code 05, its address, written data, and read data are displayed.
(6-4) IC281 (CXD1900BQ) DRAM check
IC093 (ROM) n IC281 n IC280, IC282 n NIC284 (DRAM)
n IC281 read collating check
Checking range: 0x00000000 - 0x0003ffff (data bus width = 64bits)
IC093 ROM pattern is copied to all areas to be checked. Because of
large DRAM capacity, each time 256 bytes are copied, 255 bytes of
original (IC093) address are returned. A reading check is made
after data are written to all areas.
The error code 03 when writing is not ready, or error code 04 when
reading is not ready is output, then a check is finished.
Also, if compared data are not same, a check is suspended, and
error code 05, its address, written data, and read data are displayed.
However, the data are displayed every 8 bits, though the bus width
of IC281 (CXD1900BQ) is 64 bits. Namely, actual address is the
displayed value shifted by 3 bits to the right where lower 3 bits
indicate the byte position.
For example, in the case of display shown below:
IC281 (CXD1900BQ) DRAM
Error Code: 05
Address: 000abcde
Write Data: fb
Read Data: ff
If displayed value 0 0 0 A B C D E is expressed with binary num-
ber, 0000 0000 0000 1010 1011 1100 1101 1110.
If it is shifted by 3 bits to the right, 0000 0000 0000 0001 0101 0111
1001 1011 110. That is, assuming that the top of address 0 0 0 1 5
7 9 B in hexadecimal notation is 0th byte, the 6th byte is erroneous
such as FB n FF (as for the bit position in the same manner, the
53rd bit is 0 n 1, assuming that MSB is 0th and LSB is 63rd).
(6-5) CXD1914 VSync check
IC475 (CXD1914Q) VSync interrupt cycle measurement
The VSync interruption is enabled for about 160msec, and the num-
ber of VSync interruption from NTSC encoder is counted. The op-
eration is normal if the count is more than 9 times and less than 11
times. If out of this range, the error code 41 is output.
The SCI1 interruption is also enabled, as the NTSC encoder pro-
cessing is required due to VSync interruption.
(6-6) IC281 (CXD1900BQ) VSync interrupt line check
IC281 (CXD1900BQ) VSync interrupt detection check
The VSync interruption of IC281 (CXD1900BQ) is enabled and
whether interruption is made is checked. If no interruption is made
though 2 seconds elapsed, the error code 41 is output.
(6-7) IC217 (CXD8598R) to IC281 (CXD1900BQ) connection
6-5