Sony dvp-s3000 Service Manual page 34

(5-3) IC217 (CXD8598R) register check
Register write n Register read collating check
Registers to be checked: TSC2 (0x06200011)
TSC1 (0x06200012)
TSC0 (0x06200013)
Incrementing 1 each starting from 0, data are written to readable
and writable registers, then they are read for checking. Incrementing
initial value by 1 each, a check is repeated 256 times.
If compared data are not same, a checking is suspended, and error
code 05, its address, written data, and read data are displayed.
(5-4) IC181 (CXD8663Q) reset check
Write to register n Hard reset n Read from register
Register to be checked: INTRMASK (0x22)
Data other than 0 are written to readable and writable register in
IC181 (CXD8663Q), and they are read after hard reset, then the
error code 02 is output if they are not cleared to 0.
(5-5) IC181 (CXD863Q) register check
Register write n Register read collating check
Register mask data to be checked
0x20 0xbf
0x22 0xff
0x25 0xff
0x26 0xff
0x27 0xff
Incrementing 1 each starting from 0, data are written to readable
and writable registers, then they are read for checking. Incrementing
initial value by 1 each, a check is repeated 256 times. However,
some bits that cannot be written are masked.
If compared data are not same, a checking is suspended, and error
code 05, its address, written data, and read data are displayed.
(5-6) IC181 (CXD8663Q) DRAM check
ROM n IC181 (CXD8663Q) n DRAM n IC181 (CXD8663Q)
read collating check
Checking range: 0x00000000 - 0x0007ffff
ROM pattern is copied to all areas to be checked. Each time 256
bytes are copied, 255 bytes of original (ROM) address are returned.
A reading check is made after data are written to all areas.
If compared data are not same, a checking is suspended, and error
code 05, its address, written data, and read data are displayed.
(5-7) IC181 (CXD8663Q) interrupt line check
IC093 (Syscon ROM) n IC181 (CXD8663Q) n IC217
(CXD8598R)
DVD bit stream data stored in IC093 are transferred to the IC182
(external DRAM of IC181), and the SD bus sector header detect
interruption is checked, which occurs by flowing data to the IC217
(CXD8598R).
If the header of SD bus sector in IC181 (CXD8663Q) is not
detected, the error code 31 is output.
As SERR signal from IC181 (CXD8663Q) to IC217 (CXD8598R)
is not initialized, this signal line is shut off and fixed to "high" be-
fore checking.
(5-8) IC181 (CXD8663Q) to IC217 (CXD8598R) connection check
IC093 (Syscon ROM) n IC181 (CXD8663Q) n IC217
(CXD8598R)
DVD bit stream data stored in IC093 are transferred to the IC182
(external DRAM of IC181), and IC217 (CXD8598R) transfer end
interruption is checked, which occurs by flowing data to the IC217
(CXD8598R). If the transfer end interruption is not detected, the
error code 21 is output.
As SERR signal from IC181 (CXD8663Q) to IC217 (CXD8598R)
is not initialized, this signal line is shut off and fixed to "high" be-
fore checking.
(5-9) IC184 (CXD8669AQ) reset check
Write to register n Hard reset n Read from register
Register to be checked: SYSINI (0xe1)
Data other than 0 are written to readable and writable register in
IC184 (CXD8669AQ), and they are read after hard reset, then the
error code 02 is output if they are not cleared to 0.
(5-10) IC184 (CXD8669AQ) register check
Register write n Register read collating check
Register mask data to be checked
0xe0 0x80
0xe1 0xff
0xe4 0xc0
0xe5 0xc0
0xe6 0xf8
Incrementing 1 each starting from 0, data are written to readable
and writable registers, then they are read for checking. Incrementing
initial value by 1 each, a check is repeated 256 times. However,
some bits that cannot be written are masked.
If compared data are not same, a checking is suspended, and error
code 05, its address, written data, and read data are displayed.
(5-11) IC216 (CXD1186) reset check
Write to register n Hard reset n Read from register
Registers to be checked: DADRC_L (0x06380007)
Data other than 0 are written to readable and writable register in
IC216 (CXD1186), and they are read after hard reset, then the error
code 02 is output if they are not cleared to 0.
6-4
DADRC_H (0x06380008)
HXFRC_L (0x06380009)
HXFRC_H (0x0638000A)
HADRC_L (0x0638000B)
HADRC_H (0x0638000C)