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MICROCOMPUTER'S TERMINAL DESCRIPTION
3 7 63 1515 0
Pin No.
Pin Name
7~11
D3~D7
12
CGND2
13
D8
14
D9
15
D10
16
CVCC2
17, 18
D11, D12
19
CGND3
20~22
D13~D15
23
PGND
24
CAP0
25
PVCC
26
CS0
27
CS1
28
RD
29
WE0
30
WE1
31
DACK
TE
L 13942296513
32
MODE0
33
MODE1
34
MODE2
35
TEST
36
RESET
37
CLK0
38
GND1
39, 40
A1, A2
41
VCC1
42~49
A3~A10
50
GND2
51~60
A11~A20
61, 62
A21, A22
63
GND3
64~68
MD0~MD4
69
GND4
70
MD5
71
VCC2
72~78
MD6~MD12
www
79
GND5
80, 81
MD13, MD14
82
VCC3
.
83
MD15
84
MWE
85
MRAS0
I/O
I/O
CPU data input and output
-
Ground input
I/O
CPU data input and output
I/O
CPU data input and output
I/O
CPU data input and output
-
Power supply
I/O
CPU data input and output
-
Ground
I/O
CPU data input and output
-
Ground
-
The external capacity terminal for multiplication circuit
-
Power supply
I
Chip selection 0 (UGM)
I
Chip selection 1 (internal register)
I
Lead Strobe
I
The write-in pulse 0 (low rank side)
I
The write-in pulse 1 (higher rank side)
I
DMA acknowledge
I
Mode terminal 0 of operation
I
Mode terminal 1 of operation
I
Mode terminal 2 of operation
O
Test terminal
I
Reset
I
Q2i operation clock
-
Ground input
I
CPU address input
-
Power supply input
I
CPU address input
-
Ground
I
CPU address input
-
Un-connecting
-
Ground
I/O
Memory data input and output
-
Ground
I/O
Memory data input and output
-
Power supply
I/O
Memory data input and output
-
Ground
x
ao
u163
I/O
Memory data input and output
y
-
Power supply
i
I/O
Memory data input and output
O
A memory write-in pulse
O
A low selection signal
FGZ806EF2/EOP
2 9
8
Purpose / Description / Processing / Operation
Q Q
3
6 7
1 3
1 5
co
.
9 4
2 8
0 5
8
2 9
9 4
2 8
m
9 9
9 9
11
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