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QQ
MICROCOMPUTER'S TERMINAL DESCRIPTION
3 7 63 1515 0
Pin No.
Pin Name
49
CS1
50
CS0
51~53
NC
54
CS2
55
VSS6
56
ROM RESET
57
ROM RY/BY
58
NC
59
DACK
60
NC
61
VSS7
62
DREQ
63
VCC4
64~68
NC
69
SYSCS
70
IRL
71
VSS8
72
SHCON
TE
L 13942296513
73~76
D12~D15
77
VCC5
78
D11
79
VSS9
80~84
D6~D10
85
VCC6
86
D5
87
VSS10
88~92
D0~D4
93
VSS11
94
XTAL
95
MD3
96
EXTAL
97
MD2
98
NMI
99
VCC7
100
NC
101
WAIT
102
MD1
www
103
MD0
104
PLLVCC
105
PLLCAP
.
106
PLLVSS
107
NC
108
SHRST
I/O
O
Chip selection output (inside register of Q2i)
O
Chip selection output (flash ROM)
-
Un-connecting
O
Chip selection output (Q2iUGM)
-
Ground
O
Flash ROM reset output
I
Flash ROM lady busy input
-
Un-connecting.
O
Q2iDMA transmission Strobe output
-
Un-connecting.
-
Ground input
I
Q2iDMA transmission demand input
-
Power supply
-
Un-connecting.
I
Graphic microprocessor Request-to-Send input
I
Q2i interrupt request input
-
Ground
I
Graphic microprocessor standby control input
I/O
Data bus input and output
-
Power supply
I/O
Data bus input and output
-
Ground
I/O
Data bus input and output
-
Power supply
I/O
Data bus input and output
-
Ground
I/O
Data bus input and output
-
Ground
I
Crystal oscillator input
I
Mode setting input of operation
I
Crystal oscillator input
I
Mode setting input of operation
I
Non maskable interrupt input
-
Power supply
-
Un-connecting
I
Q2i wait cycle insertion input
I
Mode setting input of operation
I
Mode setting input of operation
x
ao
u163
I
The power supply input for built-in PLL
y
I
The capacity input for built-in PLL
i
I
The grand input for built-in PLL
-
Un-connecting
I
Reset input
FGZ806EF2/EOP
2 9
8
Purpose / Description / Processing / Operation
Q Q
3
6 7
1 3
1 5
co
.
9 4
2 8
0 5
8
2 9
9 4
2 8
m
9 9
9 9
9
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