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7. CIRCUIT DIAGRAM
1
1
1
2
2
2
3
3
3
VDDIOA
VDDIOB
VDDIOC
A
A
A
C21
CPU_19.2M
MXTALI
C22
MXTALO
C19
CLK32K
SXTALI
C20
SXTALO
D20
PORN
PORN
D17
MCAM_CLK_OUT
CLKOUT0
B
B
B
VDDIOD
AP_TMS
E6
TMS
AP_TDO
C5
TDO
AP_VDD_IO_1.8V
AP_TDI
D5
TDI
VDDIOE
AP_TCK
D4
TCK
AP_TRST_N
E5
NA
TRSTN
H24
TAPSEL
R104
N22
SCANEN
D23
SCANMOD
L11
TSTCLK
D21
BATOK
VDDOK
D19
VDDOK
PWREN
E20
PWREN
E19
REMAP1_SMPREGN
F19
C
C
C
REMAP0_SMDIRN
M24
SMAD10
W21
SMPS1N
J21
SMPS0N
J22
SMCS1N
K22
SMCS0N
M23
SMAD9
L24
SMWEN
P21
SMOEN
N23
SMAD0
K23
SMAD1
L23
SMAD2
K24
SMAD3
M22
SMAD4
VDDIOD
N24
SMAD5
J23
D
D
D
SMAD6
L22
TP100
SMAD7
J24
SMAD8
R109
10K
P24
SMWAITN
Y23
SMFWPN
Y24
SMFRSTN
TP101
W22
SMA_DQ0
V23
SMA_DQ1
T23
SMA_DQ2
T22
SMA_DQ3
V24
SMA_DQ4
U24
SMA_DQ5
P23
SMA_DQ6
P22
SMA_DQ7
V22
SMA_DQ8
U23
SMA_DQ9
U22
E
E
E
SMA_DQ10
W24
SMA_DQ11
R23
SMA_DQ12
R22
SMA_DQ13
VDDIOD
T24
SMA_DQ14
R24
SMA_DQ15
EAR_SENSE_N
H23
SMPIOWN
VGA_STANDBY_AP
E18
R110
SMPIOIS16N
4.7K
AE7
TP102
TMPWNG0
AE8
TMPWNG1
AE19
VDDIOA
NANDWP0N
AE20
NANDWP01
R111
10K
HCSN_ETMCLK_XTICLK
H3
HCSN
UART_SW
G5
HALEN_SSPRXD
EBI2_ADDR(2)
H4
HADR2_URXD1
EBI2_ADDR(1)
H5
F
F
F
HADR1_UTXD1
HPI_EME_MOD_ETMPSTA1_XTIDAT
J5
HADR0
HPI_EME_APE_ETMPSTA2_XTIDAT
J4
HBHEN
EBI2_WE_N
G6
100K
HWRN_SSPFRM
EBI2_OE_N
G4
HRDN_SSPCLK
AP_RTCK
E4
R113
HRDY_RTCK
N4
HPIEV
EBI2_DATA(0:15)
HPIEV_IT_STATE_ETMTRIGIN
E12
HDAT15
EBI2_DATA(15)
C11
HDAT14_MSPSCK1
EBI2_DATA(14)
D11
HDAT13
EBI2_DATA(13)
E11
HDAT12
EBI2_DATA(12)
C10
HDAT11_MSPTFS1
EBI2_DATA(11)
D10
HDAT10_MSPTXD1
EBI2_DATA(10)
N3
HDAT9
EBI2_DATA(9)
P4
HDAT8
EBI2_DATA(8)
R4
HDAT7
EBI2_DATA(7)
R3
C
C
C
HDAT6
EBI2_DATA(6)
T5
HDAT5
EBI2_DATA(5)
TP103
T4
HDAT4
EBI2_DATA(4)
T3
HDAT3
EBI2_DATA(3)
U5
HDAT2
EBI2_DATA(2)
U4
HDAT1
EBI2_DATA(1)
U3
HDAT0
EBI2_DATA(0)
D
D
D
AP_VDD_IO_1.8V
E
E
E
5
U102
1
VCC
4
REMOTE_PWR_ON_AP
2
REMOTE_PWR_ON
GND
NL17SZ08XV5T2
3
F
F
F
1
1
1
2
2
2
3
3
3
4
LG(42)-A-5505-10:01
LG(42)-A-5505-10:01
Copyright © 2007 LG Electronics. Inc. All right reserved.
Only for training and service purposes
4
4
4
5
5
5
6
6
6
7
7
7
VDDIOD
VDDIOE
VDDIOF
VDD12
VDDNAND
VDDDDR
VDDA
VDDQ
U100
STN8810S12B2V1
AP_VDD_IO_1.8V
X100
CSC3M192000EEVRS00
4
3
VDD
OUT
1
2
REQUEST_MC
TRI_OPEN
GND
19.2MHz
C153
0.1u
4
4
5
5
5
6
6
6
7 7
7
8
8
8
9
9
9
10
10
10
11
11
11
12
12
12
AP_VFUSE
C6
KEYCODER_RSTN
GPIO3
D7
KEYCODER_INT
GPIO4
F8
PWR_BTN
GPIO5
E8
HOOK_SENSE
GPIO6
F15
MSPTCK0
GPIO19
D16
MSPRFS0
GPIO21
C16
MSPRCK0
GPIO22
C17
2M_RSTN_AP
GPIO26
D18
LEVEL_SHIFT_EN
GPIO28
C18
WLED_CTL
GPIO29
AB8
AU_PWR_EN
GPIO34
AB7
LCD_PWR_EN
GPIO35
AC7
CAM_PWR_EN
GPIO36
AD7
USB_SW
GPIO37
AD6
UTXD2
GPIO38
N6
I2CSCL1
GPIO53
N5
I2CSDA1
GPIO54
BT_RESETN
G3
GPIO58_SSPTXD
D22
2M_PWDN_AP
GPIO76
K4
HPI_IT_MOD_ETMSYNCA_XTIDAT
GPIO91
J3
HPI_IT_APE_ETMPSTA0_XTIDAT
GPIO92
D6
UTXD0
UTXD0
F7
URXD0
URXD0
E7
UCTS0N
UCTS0N
D8
URTS0N
URTS0N
AB6
URXD2
URXD2
E24
USBVP
USBVP
USBVM
F22
USBVM
F23
USBRCV
USBRCV
E22
USBSDA
USBSDA
G22
USBINTN
USBINTN
G23
USBOEN
USBOEN
E23
USBSCL
USBSCL
F5
I2CSCL0
I2CSCL0
F4
I2CSDA0
I2CSDA0
E21
IT_WAKE_UP_AP
PWLOUT
K5
CCIRID(7)
CCIRID7_CCIROD7
K3
CCIRID(6)
CCIRID6_CCIROD6
CCIRID(5)
L4
CCIRID5_CCIROD5
L5
CCIRID(4)
CCIRID4_CCIROD4
L3
CCIRID(3)
CCIRID3_CCIROD3
M4
CCIRID(2)
CCIRID2_CCIROD2
M5
CCIRID(1)
CCIRID1_CCIROD1
M3
CCIRID(0)
CCIRID0_CCIROD0
P5
CCIRIVS
CCIRIIVS
P3
CCIRIHS
CCIRIHS
R5
CCIRICLK
CCIRICLK_CCIROCLK
D9
CCPDAP
E9
CCPDAN
C9
CCPCKP
E10
CCPCKN
C8
CCPRSET
V3
DIS_CSN
CLPWR
W4
CLLPHS
V5
DIS_RS
CLPCK
AA7
LCD_VS
CLFPVS
W3
DIS_WEN
CLACDE
V4
CLLE
AC8
VGA_RSTN
CLCD17
AD8
LCD_NRESET
CLCD16
LCD_DATA(15)
AC6
CLCD15
LCD_DATA(14)
AB5
CLCD14
AC5
LCD_DATA(13)
CLCD13
AA6
LCD_DATA(12)
CLCD12
AA5
LCD_DATA(11)
CLCD11
AD5
LCD_DATA(10)
CLCD10
AC4
LCD_DATA(9)
CLCD9
AB4
LCD_DATA(8)
CLCD8
AA4
LCD_DATA(7)
CLCD7
AB3
LCD_DATA(6)
CLCD6
Y5
LCD_DATA(5)
CLCD5
AA3
LCD_DATA(4)
CLCD4
LCD_DATA(3)
Y4
CLCD3
LCD_DATA(2)
Y6
CLCD2
Y3
LCD_DATA(1)
CLCD1
W5
LCD_DATA(0)
CLCD0
L25
DU1
T25
DU2
AE25
GND63
AE26
GND64
AF24
GND65
AF25
GND66
AF26
GND67
AP_VDD_IO_1.8V
0.1u
C151
VCC
U101
5
1
PWREN
4
CPU_19.2M
2
NL17SZ08XV5T2
3
C152
GND
NA
AP_VDD_IO_1.8V
0.1u
C154
VCC
U103
5
1
AU_CLK_EN
4
AU_19.2M
2
NL17SZ08XV5T2
3
GND
8
8
8
9
9
9
- 191 -
13
13
13
14
14
14
15
15
15
16
16
16
VDDIOC
AP_VDD_IO_1.8V
VDD12
AP_VCORE
R101
R102
0
0
VDDIOD
VDDA
AP_VPLL
R103
10
VDDIOE
VDDQ
VDDDDR
VDDNAND
VDDNAND
VDDQ
VDDDDR
VDDIOE
C110
C111
C112
C113
C114
C115
C116
C117
C118
C119
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
VDD12
C120
C121
C122
C123
C124
C125
C126
C127
C128
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
VDDIOD
VDDIOE
VDDIOF
C129
C130
C131
C132
C133
C134
C135
C136
C137
LCD_DATA(0:15)
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
VDDIOC
C138
C139
C140
C141
C142
C143
C144
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
VDDIOA
VDDIOB
VDDIOA
AP_VDD_IO_2.7V
R114
0
VDDIOB
C145
C146
C147
C148
C149
C150
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
VDDIOF
Section
Date
Sign & Name
MAY
MODEL
JOY 1.3
Designer
LGE
2006
Checked
DRAWING
AP CPU & Memory
NAME
NAME
Approved
Approved
DRAWING
DRAWING
LG Electronics Inc.
LG Electronics Inc.
NO.
NO.
LG Electronics Inc.
LG Electronics Inc.
LGE Internal Use Only
A
A
A
B
B
B
D
D
D
E
E
E
F
F
F
C
C
C
C
C
C
D
D D
E
E
E
Sheet/
Sheet/
Sheets
Sheets
1/7
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