Sony Ericsson W890 Troubleshooting Manual page 84

CODEC CCO Voltage Source
There is an internal voltage source CCO that provides the necessary drive current for
electret microphones. The voltage source is I²C programmable to 2.2 V or 2.4 V. The
source can be disabled during standby. A typical use case with a microphone connected
to MIC1 and the CCO is shown in picture below.
Earphone Amplifier
The earphone amplifiers (BEARP and BEARN) are mainly intended to be differentially
configured and drive a low impedance dynamic transducer (earpiece) but they can also
be single ended configured. The BEARP and BEARN amplifiers can be powered down by the
I2C. The amplifiers can exhibit high impedance to 1.4 V or low impedance to ground when
powered-down. Fifty-one gains are available for BEARP and BEARN: from +15 dB down to –60
dB in
1.5 dB steps. When the BEARP and BEARN outputs are operating in differential mode, an I²C
selectable bit must invert one of the inputs.
FUNCTIONAL OVERVIEW Technical Description
Digital Baseband Controller (CPU)
D2000 (Anja)
This component is not replaceable on SL 4 because Baseband calibration is required.
The Digital Baseband Controller is divided in two subsystems:
Access Subsystem
All modem functionality in the digital baseband controller resides in the Access
subsystem. This includes EDGE/GPRS/GSM interface, WCDMA interface, USB, and other
peripheral modules. The control CPU is an ARM926 and a DSP is used for signal processing
and layer one control code. The main communication between the blocks in the Access
subsystem is done through the Advanced High-performance bus (AHB) matrix, which is a set
of control buses connecting the different parts together. A block called Syscon is responsible
for distributing clocks and resets to all parts of the Access subsystem. This block is under SW
control. The Access subsystem is connected to the Shared EMIF, an interface for
communication with an external SDRAM. The interface has 39 signals (including one chip
select) and supports memory sizes up to 512 Mbit. The Shared EMIF is shared between the
Access subsystem and the Application subsystem.
Application Subsystem
The Application subsystem contains functionality related to functions such as MMI,
graphics, audio and memory media. The control CPU is an ARM926 with three external
memory interfaces, one shared with the Access subsystem and two dedicated for the
Application subsystem. The Application subsystem contains several blocks. The main
communication between the blocks is done through the Advanced High performance bus (AHB)
matrix, which is a set of control buses connecting the different parts. A block called Syscon is
responsible for distributing clocks and resets to all parts of the Application subsystem. This
block is under SW control. The Application subsystem is connected to the Shared EMIF that is
used for code execution or data storage. In addition, a dedicated EMIF and a Flash IF are also
available. The Application EMIF is a general interface for communication with, for example
external SDRAM, PSRAM, NOR flash, NAND flash and companion chips. The Application EMIF
has a total of 56 signals (including a maximum of 7 chip selects if GPIO is used) and can
be set in several different modes to support different types of memory combinations.
- Application
- Access
SEMC Troubleshooting Manual
W890
1217-3942 rev. 1 84 (119)