JVC KD-SH9101 Service Manual page 46

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4.13 MN102H60KCJ1 (IC801) : LCD display sub CPU
• Pin layout
100
1
25
26
• Block diagram
Pin No. Symbol
1 RES
2 RE
3 WE
4 VCCWCNT
5 RY/BY
6 CS0
7 NC
8 SWLED4
9 SWLED5
10 SWLED6
11 NC
12 WORD
TE
13 to 16 A0 to A3
L 13942296513
17 VDD
18 NC
19 VSS
20 XI
21 XO
22 VDD
23 OSCI
24 OSCO
25 MODE
26 to 33 A4 to A11
34 AVDD
35 to 42 A12 to A19
43 AGND
44 A20
45 THERMAL
46 ANA
47 WDOUT
48 PON
49 RD
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50 LCDCLK
51 WR
.
52,53 NC
54 AVDD
55 RS
1-46 (No.49841)
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75
51
50
I/O
O LCD reset output
O Read enable output for extension memory
O Write enable output for extension memory
O Writing voltage control for external ROM
I Read/Busy input for extension memory
O Chip select1 output for extension memory
- Connect to ground
O SW_LED flashing output 4 for [PRESET1-6] key LED
O SW_LED flashing output 5 for [SEEKUP]+[SEEKDOWN] key LED
O SW_LED flashing output 6 for [DISCUP]+[DISCDOWN] key LED
- Connect to ground
I Bus width setting for extension memory (H: 8-bit width)
O Extension memory output 0 to 3
- Power supply
O Not use (Base clock output)
- Ground
I Connect to ground
O Not connect
- Power supply
I Crystal connecting terminal (25MHz)
O Crystal connecting terminal (25MHz)
I Mode setting input, pull up (H: memory extension mode)
O Extension memory output 4 to 11
- Analog power supply
O Extension memory output 12 to 19
- Analog reference power supply, connect to ground
O Extension memory output 20
I Thermal fuse input
I Audio level input for spectrum analyzer
O Watch dog timer over flow output (H: over flow)
O Power on output
O LCD read strobe output
O LCD driver clock output (300kHz)
x ao
y
O LCD write strobe output
i
- Not connect
- Analog reference power supply, connect to AVDD
O LCD regist select output
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Function
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