JVC KD-SH9101 Service Manual page 37

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• Pin function
Pin No. Symbol
1 AINL3
2 AINR2
3 AINL2
4 AINR1
5 AINL1
6 VREFH
7 AVDD
8 AVSS
9 DVSS
10 DVDD
11 XTI
12 XTO
13 CLKO
14 JX
15 SMODE
TE
L 13942296513
16 LRCLK
17 BITCLK
18 SDIN
19 SDINA
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I/O
I ADC single-ended analog Lch input pin No.3
I ADC single-ended analog Rch input pin No.2
I ADC single-ended analog Lch input pin No.2
I ADC single-ended analog Rch input pin No.1
I ADC single-ended analog Lch input pin No.1
I Analog Reference voltage input pin.
Normally, connect to AVDD (pin 7), and connect 0.1mF and 10mF capacitors between this pin and
AVSS.
- Power supply pin for analog section 3.3V (typ)
- Analog ground 0V
- Ground pin for digital section 0V
- Power supply pin for digital section 3.3V (typ)
I Master clock input pin
Connect a crystal oscillator between this pin and the XTO pin, or input the external CMOS clock sig-
nal XTI pin.
O Crystal oscillator output pin
When a crystal oscillator is used, it should be connected between XTI and XTO.
When the external clock is used, keep this pin open
O Clock output pin Outputs the XTI clock. Allows the output to be set to "L" by control register setting.
I External condition jump pin (Pull down)
I Slave/master mode selector pin
Set LRCLK and BITCLK to input or output mode.
SMODE-"L": Slave mode (These are set to input mode.)
SMODE-"H": Master mode (These are set to output mode.)
I/O LR channel select Clock pin
SMODE-"L": Slave mode : Inputs the fs clock.
SMODE-"H": Master mode : Outputs the fs clock.
I/O Serial bit clock pin
SMODE-"L": Slave mode : Inputs 64 fs or 48 fs clocks.
SMODE-"H": Master mode : Outputs 64 fs clocks.
I DSP Serial data input pin (Pull down)
Compatible with MSB/LSB justified 24 20 and 16 bits.
I DSP Serial data input pin (Pull down)
Leave opens or connect to DVSS at using the internal ADC.
Compatible with MSB justified 24 bits.
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(No.49841)1-37