Integra DTR-8.2 Service Manual page 16

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3 7 63 1515 0
ICIC BLOCK GRAM AND DESCRIPTIONS
IC BLOCK DIAGRAMS AND DESCRIPTIONS
CS493002(DSP IC)
CMPDAT,
SDATAN2
CMPCLK,
SCLKN2
CMPREQ,
LRCLKN2
SCLKN1,
STCCLK2
LRCLKN1
TE
L 13942296513
SDATAN1
CLKIN
CLKSEL
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RD,
DATA7:0,
R/W,
EMAD7:0,
EMOE,
GPIO7:0
RESET
CS
GPIO11
PARALLEL or SERIAL HOST INTERFACE
COMPRESSED
DATA INPUT
INTERFACE
FRAME
SHIFTER
INPUT
BUFFER
CONTROLLER
DIGITAL
AUDIO
INPUT
RAM INPUT
INTERFACE
BUFFER
PLL
CLOCK MANAGER
FLT2
FLT1
VA
AGND
x
ao
y
i
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8
SCDIO,SCDOUT,PSEL,GPIO9
WR,
SCDIO,
DS,
SCDOUT,
EMWR,
PSEL,
A0,
A1,
ABOOT,
GPIO10
GPIO9
SCCLK
SCDIN
INTREQ
24-BIT
DSP PROCESSING
RAM
RAM
PROGRAM
DATA
MEMORY
MEMORY
RAM
Q Q
OUTPUT
3
6 7
1 3
BUFFER
ROM
ROM
PROGRAM
DATA
MEMORY
MEMORY
STC
DGND(3:1)
VD(3:1)
u163
.
2 9
9 4
2 8
CS
18
19
INTREQ,ABOOT
20
EXTMEM,GPIO8
21
SDATAN1
22
VD3
23
DGND3
24
SCLKN1,STCCLK2
25
26
LRCLKN1
27
CMPDAT,SDATAN2
28
CMPCLK,SCLKN2
EXTMEM,
GPIO8
DD
DC
MCLK
SCLK
LRCLK
OUTPUT
FORMATTER
1 5
0 5
8
2 9
9 4
AUDATA<2.0>
XMT958/AUDATA3
m
co
DTR-8.2
9 9
6
A1,SCDIN
5
RD,R/W,EMOE,GPIO11
4
WR,DS,EMWR,GPIO10
3
AUDATA3,XMT958
2
DGND1
1
VD1
44
MCLK
43
SCLK
42
LRCLK
41
AUDATA0
40
AUDATA1
2 8
9 9

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