Integra DTR-8.2 Service Manual page 15

Hide thumbs Also See for DTR-8.2:
Table of Contents

Advertisement

QQ
IC BLOCK DIAGRAMS AND DESCRIPTIONS
3 7 63 1515 0
AK4528VF(24 bit 96 kHz Audio CODEC)
AINL+
AINL-
AINR+
AINR-
VCOM
AOUTL+
AOUTL-
AOUTR+
AOUTR-
VREF
VA
AGND
TE
L 13942296513
www
.
http://www.xiaoyu163.com
Control Register I/F
P/S
CSN
CCLK CDTI
(DIF) (CKS1) (CKS0)
No.
Pin Name
I/O
VOM
1
O
2
AINR+
I
3
AINR-
I
4
AINL +
I
5
AINL -
I
6
VREF
I
7
AGND
-
8
VA
-
9
P/S
I
10
MCLK
I
11
LRCK
I
12
BICK
I
13
SDTO
O
14
SDTI
I
CDTI
I
15
CKS0
I
CCLK
I
16
CKS1
I
CSN
I
17
DIF
I
18
DFS
I
19
PDN
I
20
DEM0
I
21
DEM1
I
22
VT
-
23
VD
-
24
DGND
-
25
AOUTL-
O
26
AOUTL+
O
27
AOUTR-
O
28
AOUTR+
O
x
ao
u163
y
i
http://www.xiaoyu163.com
2 9
8
ADC
HPF
DATT
DAC
SMUTE
Clock Divider
MCLK
Function
Common Voltage Output Pin,VA/2.
Bias voltage of ADC inputs and DAC outputs.
Rch Positive Input Pin.
Rch Negative Input Pin.
Lch Positive Input Pin,
Lch Negative input Pin.
Voltage Reference Input Pin,VA.
Q Q
Used as a voltage reference by ADC & DAC,VREF is connected
3
6 7
1 3
1 5
externally to filtered VA.
Analog Ground Pin
Analog Power Supply Pin,4.75~5.25V.
Parallel/Serial Mode Select Pin.
"L":Serial Mode,"H":Parallel Mode
Master Clock Input Pin
Input/Output Channel Clock Pin
Audio Serial Data Clock Pin.
Audio Serial Data Output Pin.
Audio Serial Data Input Pin.
Control Data Input Pin in Serial Mode.
Master Clock Select Pin.
Control Data Clock Pin in Serial Mode.
Master Clock Select Pin.
Chip Select Pin in Serial Mode.
Digital Audio Interface Select Pin,
2
"L":24bit MSB justified,"H":I S compatible.
Double Speed Sampling Mode Pin.
Power-Down Mode Pin.
"H":Power up, "L":Power down reset and initialize the control register.
De-emphasis Control Pin
De-emphasis Control Pin
Output Buffer Power Supply Pin,2.7~5.25V
Digital Power Supply Pin, 4.75~5.25V.
Digital Ground Pin
Lch Negative Analog Output Pin.
Lch Positive Analog Output PIn.
Rch Negative Analog Output Pin.
Rch Positive Analog Output PIn.
co
.
9 4
2 8
VD
VT
DGND
PDN
LRCK
Audio I/F
BICK
Controller
SDTO
SDTI
DEM0
DEM1
Block Diagram
DFS
0 5
8
2 9
9 4
2 8
m
DTR-8.2
9 9
9 9

Advertisement

Table of Contents
loading

Table of Contents