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Ja75\ _ _ _ _ _ _ _
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946261-9701
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14
15
LSB MEMORY ADDRESS
(A) 133997
Figure 3-7. Control Word 5
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4
7
8
10
11
15
SPARE
UNIT SELECT
SPARE
MSBS MEMORY ADDRESS
(A) 133998
Figure 3-8. Control Word 6
track. An attempt to transfer from a nonexistent TILINE memory results in a TILINE timeout
status for the controller. For a write command, this field specifies the record word count.
3.5.6 LSD MEMORY ADDRESS, CONTROL WORD 5. The least significant bit (LSB) memory
address is determined by control word 5 (Figure 3-7). By the use of this control word, the software
selects the 15 least significant bits (LSB) of the TILINE memory address for the starting address of a
data transfer. The controller fetches or stores data through the TILINE bus at sequential addresses
until the word count decrements to zero. The CPU byte selection bit (bit 15) is ignored by the
controller.
3.5.7 UNIT SELECT AND MSD MEMORY ADDRESS, CONTROL WORD 6. The disk drive
selected and most significant bit (MSB) memory address are specified by control word 6 (Figure
3-8). Bits 0 through 3 and 8 through 11 of this field are not used.
Bits 4 through 7, Unit Select Field. The value of this field is used to select one of four disks (one
fixed and one cartridge for each of two disk drives) attached to the disk controller. Only one disk
drive can be selected at a time, as follows:
Bit 4 - Disk drive 0, fixed disk
Bit 5 - Disk drive 0, cartridge disk
Bit 6 - Disk drive 1, fixed disk
Bit 7 - Disk drive 1, cartridge disk.
Bits 11 through 15, MSB Memory Address. This field selects the five most significant bits of the
TILINE memory address. These 5 bits are concatenated to the 15 LSB memory address bits of con-
trol word 5 to complete the 20-bit TILINE address.
3-7
Digital Systems Division
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