Panasonic EURO 4 Chassis Technical Manual page 53

17.10.2.Deflection Processing
The deflection processing section is used to
generate the signals for the horizontal and vertical
drive. This block contains two phase-locked loops.
1. PLL2 is used to generate the horizontal and
vertical timings, this is achieved with the aid of
the front sync signal (FSY) which is used to
synchronise phase and frequency. Also input to
PLL3 is the Horizontal flyback pulse (HFLB)
which is used to synchronise the processing of
the horizontal drive output signal.
The signal output from PLL2 is used to generate
the E/W output fed from pin 32 of
vertical output which is fed via pin 31 again of
IC601.
2. PLL3 is used to adjust the phase of the horizontal
drive pulse which compensates for the delay of
IC601 and the
53
the horizontal output stage, the horizontal output
being fed via pin 50 of
The horizontal drive circuitry uses a digital sine
wave generator to produce an exact (subclock)
timing for the drive pulses. The generator which
runs at 1MHz, in the output stage divides down
this frequency to produce the drive pulse.
In standby mode the output stage is driven by an
internal 1MHz clock which is derived from the
20.25MHz main clock oscillator, connected to
pins 51 and 52 of the VDP IC601. Here the
20.25MHz clock frequency is divided down by an
internal frequency divider which is set to a fixed
divider ratio during this period. However when
the circuit is switched out of standby mode the
frequency divider is switched to a programmable
divider mode.
3DQDVRQLF
IC601