Panasonic EURO 4 Chassis Technical Manual page 52

3DQDVRQLF
17.10.Synchronisation and Deflection
The synchronisation and deflection processing is
output from the Front and Back End processors.
The video clamping, horizontal and vertical sync
separation and all video related timing information
are processed in the front end.
Most of the processing that runs at the horizontal
frequency is programmed by the internal Fast
Processor (FP). The fast processor also calculates
the values for vertical and East-West deflection.
The information extracted by the video sync.
processing is multiplexed onto the front sync. signal
(FSY) and distributed internally to the rest of the
video processing system.
17.10.1.Video Sync Processing
The block diagram of front end sync processing
shown below is used to extract the sync information
from the video signal, a lowpass filter is used to
eliminate all noise and video content above 1 MHz.
2. The second path, which has the clamping and
signal measuring circuit, is used to measure the
back porch of the signal as well as the maximum
and minimum levels of the video signal. This
information is then processed by the fast
processor and used for gain control of the
clamping circuit in the front end processor
mentioned previously.
The sync is then separated from the video signal by
a slicer, from the output of the sync slicer the signal
splits into 3 paths.
The first path is fed to Phase lock loop 1(PLL1) for
horizontal sync processing, the second path is fed to
a clamping and signal measuring circuit, while the
third path is fed to the vertical sync separation
circuit.
1. The 1st path feeds the sliced sync signal to the
horizontal sync separator before being fed to the
phase comparator and lowpass filter, here the
sync. phase error signal is filtered under the
control of the fast processor.
All timing in the front end is derived from the
counter which is also part of the PLL1. The
counter counts synchronously keeping the
processing in sync with the video signal. The
sync signal is then output via the front sync
generator as the front sync. signal (FSY).
3. The third path is fed to the vertical sync
separator, where the sliced video signal is
integrated. The fast processor uses this
integrated value to derive the vertical sync and
field information.
The data for the vertical deflection, sawtooth and
the East-West correction signal, are calculated in
the fast processor. This data is then buffered in
a FIFO memory device and transferred to the
back end by a single wire interface.
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