Panasonic EURO 4 Chassis Technical Manual page 42

3DQDVRQLF
17.3. Video Processing
17.3.1.Analogue Input
The Front End block provides an analogue interface
to all video inputs and mainly carries out analogue to
digital conversion for the following digital video
processing. A block diagram of this section is shown
below.
Most of the functional blocks in the front end are
digitally controlled (clamping, AGC and clock-DCO).
The control is carried out by a Fast Processor (FP)
which is embedded in the decoder.
The VDP3120 IC601
available which are AC coupled, these inputs being
pins 60, 61, 62. 63. 64 which are then fed to an
internal multiplexer which is used to select between
the following inputs.
:
Pin 60 (Cin) is used for the input of the
chrominance component from an S-VHS
source which is input via pin 15 of AV2 or the
AV3 S-VHS ( Wide Screen Models ONLY )
input terminal.
:
Input via pin 61 Vin1 is the standard video
signal fed from the tuner.
:
Pin 62 (Vin2) is the input for the video signal
fed from AV1 pin 20.
has up to 5 analogue inputs
: The Input via pin 63 (Vin3) is the input for the
video signal fed from AV2 pin 20, or the
Luminance input from an S-VHS source
which may be fed from AV2 pin 20.
:
The Input via pin 64 (Vin4) is the input for the
video signal fed via the RCA input of AV3
( Wide Screen Models ONLY ), or the
Luminance input from the S-VHS 4 pin input
of AV3 ( Wide Screen Models ONLY ).
The input signals mentioned above are fed to the
VDP3120 IC601
multiplexer, which is controlled by the I
before being passed on to the next stage.
The video signal is then fed to a clamping circuit
which is used to apply a clamping pulse to the back
porch of the signal. This clamping pulse is used to
ensure that the input signal is within the working
range of the A/D converter, this is also true for the
luminance component of an S-VHS input which also
follows the same path as the video signal.
When an S-VHS chrominance signal is input, the
chroma signal is fed to a clamping circuit 2 in the
chroma path, again the signal is kept within the
working range of the A/D converter, by biasing the
chrominance signal to the centre range of the A/D
converter.
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and passed via the internal
2
C bus 1,