1. Manuals
  2. Brands
  3. Panasonic Manuals
  4. TV
  5. EURO 4 Chassis
  6. Technical manual

Panasonic EURO 4 Chassis Technical Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Order No. TZS8EL001
Technical Guide

Colour Television

EURO 4 Chassis
Circuit Explanations
3DQDVRQLF
(XURSHDQ 7HOHYLVLRQ 'LYLVLRQ
0DWVXVKLWD (OHFWULF 8. /WG

Advertisement

Table of Contents
loading

Related Manuals for Panasonic EURO 4 Chassis

Summary of Contents for Panasonic EURO 4 Chassis

  • Page 1: Colour Television

    Order No. TZS8EL001 Technical Guide Colour Television EURO 4 Chassis Circuit Explanations 3DQDVRQLF (XURSHDQ 7HOHYLVLRQ 'LYLVLRQ 0DWVXVKLWD (OHFWULF 8. /WG...

  • Page 2: Table Of Contents

    3DQDVRQLF CONTENTS Introduction ........... . Power Supply Block Diagram .

  • Page 3: Introduction

    Service Manuals for this chassis. needs to understand the circuitry inside the TV and for As the Technical Guide for the Euro 4 chassis covers this need, we have produced this Technical Guide. such a wide range of models, some differences occur...
  • Page 4 Y - BOARD E - BOARD Q852 D867 Q855 Q2702 R2714 C - BOARD T2701 AUDIO D868 Q853 Q854 Model Specific OUTPUT Q2701 R2715 D862 T802 RL801 R854 T801 D801 200V -18V Line Filter IC2702 D850 R802 Q850 DEGAUSS COIL -14V K - BOARD TUNER...
  • Page 5 E - BOARD H - BOARD TUNER IC3401 SCL SDA VIDEO IC2101 SWITCHING AUDIO IC601 SDA 1 PROCESSOR VIDEO PROCESSOR SCL 1 SERVICE / TEST K - BOARD SDA 1 IC2401 SCL 1 Dolby Processor SDA 2 VPROT SCL 2 LOCAL N - BOARD KEYSCAN...
  • Page 6 E - BOARD Model Specific Q908 Q906 COILS Q905 Q907 Q909 IC601 61 V IN Q950 Q951 Q104 IC351 SVM OUT 34 VIDEO PROCESSOR B OUT 39 Q353 43 B IN Q105 OUTPUT 42 G IN G OUT 38 41 R IN R OUT 37 Q301 Q302...
  • Page 7 E - BOARD TUNER IC251 IC2101 AUDIO AUDIO OUTPUT PROCESSOR DACM_R 24 Q2102 Model Q252 Specific HEADPHONE Q103 X101 DACM_L 25 Q2103 L 11 & X102 Q251 Model SC3_IN_L 37 Specific SC3_IN_R 38 Q101 44 MONO IN 1 R OUT SC1_OUT_R 30 49 ANA_IN2+ SC1_IN_R 42...
  • Page 8 E - BOARD To K3 IC2101 I2S_DA_IN_2 18 I2S_DA_IN_2 I2S_DA_IN_1 12 I2S_DA_IN_1 I2S_DA_OUT 11 I2S_DA_OUT I2S_DA_WS 10 I2S_DA_WS I2S_DA_CL 9 I2S_DA_CL TUNER 44 MONO IN DACM_R 24 Q2102 IC251 Q252 Q103 49 ANA_IN2+ DACM_L 25 L 11 Q2103 Model Specific Model Specific Q251 X101...
  • Page 9 Q2705 JK2702 IC2704 K-Board Q2704 Surround L Q2703 Centre Surround R IC2703 Centre Surround Q2422 Q2423 Q2432 Q2425 IC2702 Woofer Q2426 Q2428 Q2427 Q2424 C-Board To E12 I2S_DAOUT_2 JK2401 IC2401 Q2403 Surround R Q2404 Q2405 Q2406 I2S_DA_OUT_1 Q2419 Q2401 Q2402 I2S_DA_IN Surround L Q2418...

  • Page 10: Power Supply

    3DQDVRQLF POWER SUPPLY The supply voltage in the EURO 4 chassis is 8.1. Standby Power Supply Circuit provided by the integrated circuit STR-F6654. The standby transformer T802 has the A.C. supply As well as the main power supply a standby power as just mentioned being fed via the primary winding supply is also used.
  • Page 11 3DQDVRQLF The first path sees the supply voltage being The second path is via resistor R862 to the fed via resistor R861 to the standby relay base of transistor Q852. This supply being RL801 and the relay winding to the collector regulated by the zener diode D872 is used of transistor Q853.
  • Page 12 3DQDVRQLF 8.2. Flyback Converter Power Supply The STR-F6654 is a hybrid IC with built-in features pulse-by-pulse overcurrent MOS-FET and control IC as well as a separate protection, over-voltage protection (with latch) and oscillation circuit. thermal protection functions. 8.2.1. General It features a small SIP (Single In-line Package) with The mains voltage flows through the mains isolated body (no bush and micra isolator required) suppression filter and standby relay, before being...
  • Page 13 3DQDVRQLF 8.3. Start Up Circuitry The start-up circuit is used to start and stop Once IC801 begins to operate the supply voltage at operations of the control IC IC801, by detecting the pin 4 is supplied via the rectifying diode D803 and voltage appearing at the Vcc terminal, pin 4.
  • Page 14 3DQDVRQLF 8.4. Operation 8.5. Regulation When the internal MOS-FET transistor of IC801 The power supply ON time is controlled by conducts the current flows via the primary winding controlling the feedback supply to pin 1 of IC801. P1 / P2 of T801 and IC801 pin 3 (Drain) and pin 2 This is achieved by the use of the photocoupler...
  • Page 15 3DQDVRQLF 8.6. Protection Circuitry In this condition the Vcc input (pin 4) voltage decreases until the the Vcc input reaches the 8.6.1.Thermal Shut-down shut-down voltage of 10V. At this point pin 4 begins This circuit triggers the latch circuit when the body of to rise again but when it reaches the start up level •...
  • Page 16 3DQDVRQLF 8.7. Secondary side On the secondary side the transformer supplies the A 15V supply which is fed from the following voltages : transformer T801 is fed to pin 1 of IC851 150V to supply the line output stage which is used to produce a stabilized 12V supply.
  • Page 17 3DQDVRQLF HORIZONTAL/VERTICAL OUTPUTS 9.1. Horizontal Driver control. The driver stage is fitted with a transistor which is able to supply the necessary base control The line frequency control pulses for the horizontal current of up to 0.9 Amps for the driver transformer driver stage are output via pin 50 of the VDP IC601 T501 of the output stage.
  • Page 18 3DQDVRQLF 9.2. Horizontal Output Stage Control of the horizontal output stage, or to be more mode. In principle, the pulse duty factor of the base precise, the horizontal switching transistor, is drive has been altered from 12 S flyback time and achieved as explained in the previous section.
  • Page 19 3DQDVRQLF 9.3. East/West Correction To compensate for the pincushion distortion in to buffer transistor Q701 before being input via pin 7 • east/west direction in the case of 110 sets, the of the East / West IC. IC701. horizontal deflection current must be increased at Here the parabola waveform is fed to a comparator, vertical centre in relation to vertical start and vertical where the parabola waveform is compared with the...
  • Page 20 3DQDVRQLF 9.4. Vertical Output Stage To drive the vertical output stage, the drive pulse is During vertical sweep, the bootstrap capacitor C456 output from the VDP IC601 pin 31 and fed to the is charged up to almost supply voltage via D454. vertical output stage IC451 pin 5.

  • Page 21: A.f. Output Stage

    3DQDVRQLF 10. AF. OUTPUT STAGE Both amplitude controlled AF signals are output from 10.1. Active Mute pins 24 and 25 of IC2101 of the MSP. The active mute circuit is used in parallel to the inputs of the audio output IC IC251. This active mute circuit consists of two transistors Q251 Q252...

  • Page 22: Colour Output Stage

    3DQDVRQLF 11. COLOUR OUTPUT STAGE The Y-Board, contains not only the colour output Transistors Q908 Q909 then outputs the signal stage, but also scan velocity modulation (except at approximately 35Vpp, via connector Y6 pins 1 model TX-21MD4 which has no SVM stage). and 3 to the SVM coils, the scan coils being controlled directly from the collector terminals of The RGB signals fed to the colour output stage are...
  • Page 23 3DQDVRQLF 11.3. Tube and Picture Measurement This circuit is arranged so that as the beam current increases transistor Q552 switches OFF, this means that resistor R564 is no longer in parallel with R262 / Tube and Picture measurements are carried out by R263 thus reducing the above mentioned artifacts.

  • Page 25: Rf/If Section

    TV standards. For this reason the stage is referred to as the multi-standard IF stage. (1) A high input impedance. (2) Low radiation from tuner. The IF stage for the EURO 4 chassis comes in 2 versions as follows: (3) Low oscillator interference. LA7577...

  • Page 27: Microprocessor And Teletext Processing

    3DQDVRQLF 13. MICROPROCESSOR AND TELETEXT PROCESSING The microprocessor SDA5450 IC1101 used on 256 bytes on-chip RAM EURO4, not only performs the required control 10kbytes on-chip display RAM processing but also teletext processing which is 1 kbyte on-chip ACQ-buffer-RAM incorporated within microprocessor, processing of which will be looked at later.
  • Page 28 3DQDVRQLF 13.1. Microprocessor Stage 13.1.1.Input Control Pins 3/4 - XIN / XOUT reset IC IC1105 inputs a reset pulse via pin 54 of the The internal oscillator of the CPU is synchronised with microprocessor IC1101. an external 6MHz quartz crystal X1101 which is Pin 58 - Slow1 / Pin 59 Slow2 connected to pins 3 and 4.
  • Page 29 3DQDVRQLF Pin 60 - Keyscan Pin 68 - CVBS In The local control commands are fed to the This composite video signal which is input via microprocessor IC1101 as serial data. This data is pin 68 is used for teletext processing which is carried input via pin 60.
  • Page 30 3DQDVRQLF Pin 75 - Prot1 :KHUH DQ HUURU GHVFULEHG DULVHV DQG WKH EHDP The microprocessor IC1101 pin 75 which is normally FXUUHQW FRQWLQXHV WR ULVH WKHQ WKH ]HQHU GLRGH ' held High via R1149 provides a protection input which FRQGXFWV GXH WR WKH QHJDWLYH YROWDJH IHG EDFN IURP is used to switch the TV into standby mode.
  • Page 31 3DQDVRQLF 13.1.2.Output Control Pins 9, 10, 12 - 22, 24 - 27, 29 - A17 - A0 reset control line output from pin 53 of the These address lines are used to address the EPROM microprocessor IC1101. During switch ON the digital IC1102 as well as the memory location for storing or ICs are held LOW by...
  • Page 32 3DQDVRQLF Pin 77 - G.M.C ( Wide Screen 32’’ Only ). the pin is set to a HIGH level which causes Q1052 Q1062 on the M-Board ) to switch ON Output from pin 77 of the microprocessor IC1101 the E-Board ( Geo-Magnetic Correction control, this is used for 16:9 causing the standby LED to light up.
  • Page 33 These above features will only work with a Where data is fed from the TV to the VCR the Panasonic TV / video combination who are both AV_Link_OUT control line fed from pin 72 of the Q-Link (Project 50+) compliant.
  • Page 34 3DQDVRQLF 13.1.4.I C Bus Pin48,49-SCL1,SDA1 / Pin 50, 51-SCL2, SDA2 7KH , & EXV LV D WZR ZLUH %86 V\VWHP FRQVLVWLQJ RI 6&/ D GDWD OLQH DQG D FORFN OLQH 7KLV %86 V\VWHP DOORZV 6ODYH 6ODYH 0DVWHU 0DVWHU 6ODYH 5HFHLYHU 7UDQVPLWWHU 7UDQVPLWWHU 7UDQVPLWWHU...
  • Page 35 3DQDVRQLF 13.2. Teletext Processing Stage General Programme Signal (VPS). The VPS feature is not used. already briefly mentioned earlier microprocessor performs teletext processing as Display Timing which is used to ensure that the well as Control processing. To perform teletext text information is locked to the same timing as the processing the following elements are required: raster scan.
  • Page 36 3DQDVRQLF 13.2.1.Teletext Operation To enable teletext processing by the microprocessor When the TTX data is requested the information is IC1101 a CVBS signal is input via pin 68. Here the read out of the Display RAM via the interface and signal is fed to the Teletext (TTX) slicer stage, where fed to the Display Generator.
  • Page 37 3DQDVRQLF 14. MEMORY I.C. (EAROM) Together with the system data for the digital IC’s, The address word is checked for compatibility with customer data is also stored in the EAROM IC1103. the address contained in the IC and acknowledged by an acknowledgement bit. The memory location address is then transmitted by The stored data includes programme location data the master I.C.

  • Page 38: Eprom

    Q0 to Q7. The in the EPROM IC1102 in the EURO 4 chassis. memory address from which the data will be read out is transmitted beforehand via lines A0 to A17. The I.C. has a memory capacity of 2Mbits, the data...

  • Page 39: Control Of The Digital Section

    3DQDVRQLF 16. CONTROL OF THE DIGITAL SECTION The digital processing on EURO 4 is controlled and data. The latter may be changed at any time by the monitored microprocessor (SDA5450) customer and these changed values stored in the IC1101. For this purpose it is connected to the signal non-volatile memory with the use of the memory processors in the digital section by means of the I function.

  • Page 40: Video Display Processor (Vdp)

    3DQDVRQLF 17.Video Display Processor (VDP3120) 17.1.Introduction Adaptive comb-filter for separation of the luma and chroma signals. The EURO4 chassis uses 3 variants of the VDP Scaler stage which is used for wide screen IC601, these variants being dependant on the models, providing the required sizing of the model, as a result the VDP3120 with the full range of picture for display on 16:9 CRTs.
  • Page 41 3DQDVRQLF 17.2. Features The VDP3120 IC601 is a high-quality single-chip Soft Limiter (gamma correction) video processor which performs the entire video Colour transient improvement display and deflection processing for 4:3 and 16:9 50/60Hz TVs. RGB Processing Programmable RGB matrix This I.C. which is used to build the heart of a modern colour TV contains the following features : digital colour bus interface additional analogue RGB / fast blank input...
  • Page 42 3DQDVRQLF 17.3. Video Processing 17.3.1.Analogue Input The Input via pin 63 (Vin3) is the input for the video signal fed from AV2 pin 20, or the The Front End block provides an analogue interface Luminance input from an S-VHS source to all video inputs and mainly carries out analogue to which may be fed from AV2 pin 20.
  • Page 43 3DQDVRQLF The video / luminance signals output from the clamp From the output of the amplifiers the video / circuits then split into 2 paths. The one path feds the luminance and chroma signals are fed to the A/D video / luminance signal to the VDP IC601 video out converters where the signals, with a clock rate of...
  • Page 44 3DQDVRQLF 17.4. Adaptive Comb Filter Introduction The comb filter also reduces interferences like cross-luminance and cross-colour artifacts without The digital CVBS signal fed from the previous introducing new artifacts or noise. front-end stage is fed to the adaptive comb filter stage which is used to produce high-quality luminance/chrominance separation for PAL or NTSC Where an S-VHS signal or SECAM signal is input...
  • Page 45 3DQDVRQLF 17.5. Colour Decoder In the colour decoder stage the standard luminance 17.5.1.Digitised Composite Video Processing chrominance separation and multi-standard The video signal which is fed to the colour decoder colour demodulation is carried out. The colour section as 8 bits of information is split into 2 paths . demodulation uses an asynchronous clock, thus Luminance Processing allowing a unified architecture for all colour...
  • Page 46 3DQDVRQLF 17.5.3.Chrominance Processing The second path that the digitised composite video During SECAM decoding the frequency of the burst signal is fed to is the chrominance processing circuit. is measured, thus the chroma carrier frequency can be identified and used to control the SECAM First of all the video signal is fed via multiplexer1 processing.
  • Page 47 3DQDVRQLF 17.6. Scaler Stage The luma and chroma signals output from the colour scaler itself contains programmable decoder are fed to the following scaler stage and the decimation filter, a 1-line delay FIFO memory and a Skew filter. programmable interpolation filter. The controlling of the scaler being performed by the 17.6.1.Skew Filter internal Fast Processor.
  • Page 48 3DQDVRQLF 17.7. Display Processor The Display processor is used to carry out the Once the signal has been output from the soft limiter conversion from digital (YC ) to digital (RGB). the luma signal is fed to the matrix circuit for In the luminance processing path, the luminance production of the RGB signals.
  • Page 49 3DQDVRQLF RGB signals are then output as 10 bits of Also included in the display processor stage of the information. The same multipliers are also used to IC601 is the picture frame generator, which is implement a software beam current control which used where the picture does not fill the total area of will be mentioned later.
  • Page 50 3DQDVRQLF $QDORJXH %DFNHQG qvt TWH D ' iv‡968 hhy‚tˆr "# ''€6 TWH Pˆ‡ (#€6 ( iv‡ ( iv‡ iyhxvt qvt S v  iv‡ hhy‚tˆr "& ‰vqr‚ S ‚ˆ‡ ( iv‡ ( iv‡ iyhxvt qvt B v  iv‡ hhy‚tˆr "' ‰vqr‚...
  • Page 51 3DQDVRQLF 17.9. CRT Measurement and Control EHDP FXUUHQW 6HQVH 0$'& 56: 7XEH 0HDVXUHPHQW &XWRII  :KLWH GULYH 3LFWXUH 0HDVXUHPHQW $FWLYH SLFWXUH 0$;  0,1 FXUUHQWV 7XEH 0HDVXUHPHQW Finally the analogue backend is also equipped with as well as R658 thus keeping the measured value in A/D converter which is used to perform Tube and the range of the A/D converter.
  • Page 52 3DQDVRQLF 17.10.Synchronisation and Deflection The synchronisation and deflection processing is The sync is then separated from the video signal by output from the Front and Back End processors. a slicer, from the output of the sync slicer the signal The video clamping, horizontal and vertical sync splits into 3 paths.
  • Page 53 3DQDVRQLF 17.10.2.Deflection Processing The deflection processing section is used to the horizontal output stage, the horizontal output generate the signals for the horizontal and vertical being fed via pin 50 of IC601 drive. This block contains two phase-locked loops. The horizontal drive circuitry uses a digital sine wave generator to produce an exact (subclock) PLL2 is used to generate the horizontal and timing for the drive pulses.
  • Page 54 3DQDVRQLF 17.10.3.Protection Circuitry As well as all the functions just mentioned picture The main oscillator and horizontal drive circuitry tube and drive stage protection are also provided. are run from a separate (standby) power supply, This is achieved through the following measures . which ensures the main oscillator and horizontal drive circuitry are already active when the TV set Vertical protection safety input pin 11: This...

  • Page 55: M-Board Processing

    3DQDVRQLF 18. M-Board Processing These left and right audio signals are also input via 18.1. General AV3 and the two RCA sockets. These left and right The M-board on EURO 4 is used on Wide Screen audio signals are then fed to the E-Board via models only and allows the input of an S-VHS video connectors M2 pins 8 and 10 and E17.
  • Page 56 3DQDVRQLF 18.1.1.Video Signal Path The composite video signal input via the RCA When the mix switch control is HIGH both terminal of AV3 is directly fed to connector M2 pin 6 transistors Q3205 Q3206 conduct. At the and to the E-Board via connector E17. Here the collector of Q3206 the chrominance signal follows...

  • Page 57: Av Switching

    3DQDVRQLF 19. AV Switching AV switching on EURO 4 is performed on the Those models without the previously mentioned H-Board, where switching IC IC3401 can be found. M-Board (non Wide Screen models) feeds the signal This switching IC being used to feed video out to the selected for output via AV2 from the VDP IC601 AV2 scart socket.

  • Page 58: Audio Signal Processing

    3DQDVRQLF 20. AUDIO SIGNAL PROCESSING 20.1.Introduction MSP3410D IC2101 designed processed analogue AF-out, within a single chip Multi-standard Sound Processor for processing of which covers all European TV standards. As well as analogue and digital audio signals. The MSP3410 processing of the analogue audio signals the IC2101 provides full TV sound processing, starting MSP3410D...
  • Page 59 3DQDVRQLF The MSP3410 IC2101 is designed to simultaneously 10. Two Digital inputs and one output via I S Bus for perform digital demodulation and decoding of external Digital Signal Processing (DSP) NICAM-coded TV stereo sound, as well as processing for features such as Surround Sound demodulation of FM-mono TV sound.
  • Page 60 3DQDVRQLF 20.2. Demodulator stage 20.2.1.Analogue Sound I.F. - Input The tuner/IF stage located on the main pcb demodulated in the I.F. stage before being passed to (E-Board) feeds the SIF signal, either Wagner the MSP3410 IC2101. The A.M. demodulated sound is then fed to the MSP IC2101 via pin 44.
  • Page 61 3DQDVRQLF When Wagner stereo, which is a 2 carrier system, is 20.2.2.Clock Generator transmitted identification signal also transmitted along with the second sound carrier. To aid processing an external crystal is connected to This identification signal which is a 54.7KHz pins 51, 52 of the MSP3410 IC2101 this provides the...
  • Page 62 3DQDVRQLF To switch the TV set to the actual sound mode, Input Pre-processing control information on the NICAM mode and bit error Channel Selection rate are supplied by the NICAM - Decoder via Channel Post-processing C bus 1 to the microprocessor IC1101. The microprocessor IC1101 then, as mentioned for FM...
  • Page 63 3DQDVRQLF 20.3. I S Bus Interface The standardised I S Bus interface allows, for S_CL: additional feature processors to be connected to the Synchronises the transmission of I S serial data MSP3410D IC2101, such as the surround processor (1.024MHz). for Dolby Pro Logic Processing which is performed S_WS: by DPL3520 IC2401 located on the K-Board (ONLY The I...
  • Page 64 3DQDVRQLF 20.3.1.A.M. and Scart Processing As mentioned at the start of the section on via pins 37 - 42. The selected audio signals are then MSP3410 IC2101 processing, when receiving an fed via two A/D converters before being input to the A.M.
  • Page 65 3DQDVRQLF 20.4. Audio Output 20.4.1.Loudspeaker Output Path via the I C bus 1. The volume modifications which occur during bass and treble adjustments are When a signal source has been selected by the user stabilised by limiting the internal volume, to prevent for output via the loudspeaker the signal is fed via a clipping, this limitation is carried out via software.
  • Page 66 3DQDVRQLF 20.4.4.Spartial Effects the volume and balance control circuits. Once again the various adjustments are carried out via the The Spartial effects depend upon the source signal, remote control with the adjustment settings being if the source signal is mono then a Pesudo stereo displayed on screen, the signals are then buffered effect can be used.
  • Page 67 3DQDVRQLF 21. History Of Dolby Pro Logic 21.1. General For over a decade from Star Wars to Dance with to as active decoders, uses a centre channel as well Wolves, Dolby Stereo has delighted cinema as the front left, right and surround channels. audiences with multi-dimensional sound.

  • Page 68: Pro Logic Processing Overview

    Centre and Surround channels additional external amplifies and speakers are required. The Panasonic TV can also be used in Phantom The normal listening function used without these mode which does away with the centre speaker...
  • Page 69 3DQDVRQLF 23. Encoding and Decoding Concepts 23.1. Dolby Surround Encoding If we look at the Dolby matrix encoder we can see that independent. Not so obvious is that there is also no the encoder accepts four separate input signals; left, theoretical loss of separation between the centre and centre, right and surround (L, C, R, S) and creates two surround signals.
  • Page 70 3DQDVRQLF 23.2. Dolby Pro Logic Decoding Dolby Surround decoders are designed to decode the allows the user to change the program balance to specially encoded audio sound-tracks of Dolby correct for channel balance errors that may exist in Surround video productions. The decoders can then the incoming audio signal, this is vital to ensuring that provide front...
  • Page 71 3DQDVRQLF 23.2.1.Adaptive Matrix Control Stage For these reasons Pro Logic has been designed to sense the level of dominance in the sound-track. To separate the Centre and Surround signals, resulting in the minimum amount of cross talk, the 23.2.2.Surround channel Processing. signals are separated by a mathematical processes, Surround channel processing for the passive and this provides directional enhancement which creates...

  • Page 72: Dolby Pro Logic Processor (Dpl3519A)

    3DQDVRQLF 24. Dolby Pro Logic Processor (DPL3519A) 24.1. Introduction The DPL3519A IC2401 is designed as a stand alone almost the same as for the MSP3400 IC2101 with the Dolby Surround Pro Logic decoder. It can also be volume and tone controls using the same registers used as a co-processor with the MSP3410 / and values.
  • Page 73 3DQDVRQLF 24.2. Features The DPL3519A IC2401 which provides a number of Identical treble/bass/loudness function for features performs the following functions: L,C,R,S 5-band equalizer for C channel Full Dolby Surround Pro Logic Adaptive Matrix Separate volume control for two surround outputs Pseudo surround mode for signals not encoded in Dolby surround Mode control : normal/phantom/wide/three...
  • Page 74 3DQDVRQLF 24.3. Dolby Pro Logic Operation 24.3.1.Audio Input signals are fed via a prescaler which adjusts the volume of the audio signal, thus ensuring the signals To perform Dolby Pro Logic processing the audio are at the same level. signals are fed between the DPL3520 IC2401 and the MSP3410...
  • Page 75 3DQDVRQLF 24.4. Digital Signal Processing (DSP) Stage 24.4.1.Dolby Pro Logic Processing When Dolby Pro Logic Active mode (Normal Mode) is selected the left (L) / centre (C) / right (R) and As already mentioned the DPL3519A IC2401 also surround (S) signals are output from the Surround performs Dolby Pro Logic processing.
  • Page 76 3DQDVRQLF In addition to the above mentioned processing to 24.4.3.Channel Output Path reproduce the Dolby Pro Logic Active or Passive signals additional external amplifiers for the Centre :KHQ RQH RI WKH IROORZLQJ VLJQDO VRXUFHV KDV EHHQ and surround signals are required. The front left and VHOHFWHG E\ WKH XVHU WKH VHOHFWHG DXGLR VLJQDO LV right signals use the internal TV speakers, ideally RXWSXW YLD RQH RI WKH IROORZLQJ FKDQQHO RXWSXW SDWKV...
  • Page 77 3DQDVRQLF 24.4.4.Bass and Treble adjustments 24.4.5.Noise Sequencer As mentioned earlier a noise generator is also The Bass and Treble adjustments consist of two contained in the DPL3519A IC2401, which in normal separate filters. The control range of the bass filter is operating conditions is switched OFF.
  • Page 78 3DQDVRQLF 24.5. Dolby Pro Logic Processing Path The Dolby Pro Logic active processing as mentioned board, the C-Board is used. For those models without earlier results in 4 channels being output in the form the C-Board an external amplifier is required. of L/R/C and S, 5 channels for those models with This centre signal which is output from pin 25 of Super 3D Bass.
  • Page 79 3DQDVRQLF 6XUURXQG $XGLR 2XWSXW for bass reproduction are fed via Q2428, which again has a muting transistor Q2427 in its base. The As with the centre channel the surround channel also Super 3D Bass signal is then fed via connector K5 requires an additional amplifier.

  • Page 80: C-Board Processing

    3DQDVRQLF C-Board Processing T2701, IC2701 containing a switching and stabilising 25.1. Power Supply circuit. 2.1. Operation Primary Side The power supply starting current is fed via resistors Located on the C-Board is the internal amplifiers for R2702 and R2703 to IC2701 pin 2, which causes Q3 the Centre, Surround and Super 3D Bass channels.
  • Page 81 3DQDVRQLF 25.1.1.Regulation Regulation is achieved through the feedback decreases reducing the bias on Q1 which in turn increases the base bias of Q3, increasing the winding F1.F2 of T2701. This feedback winding current flow. supplies a negative voltage via D2708 and R2705 to pin 1.
  • Page 82 3DQDVRQLF 25.2. Secondary Side 25.2.1.Audio Power Supply the amplifiers TDA2030 when under load, the supply voltage has to be reduced, this is achieved by reducing the +18V supply rail thus reducing the This supply is used to fed the rear / centre and overall supply voltage of TDA2030.
  • Page 83 3DQDVRQLF 25.3. Power ON/OFF Mute During switch ON/OFF times the audio signals are Q2416 is also fed the switch ON mute signal, which is then used to mute the L, R, C, and S signals muted to prevent POP. This muting is achieved at being fed to the phono outputs, this muting being switch ON by the muting circuit located on the carried out by Q2417, Q2418, Q2419,...
  • Page 84 Order No. TG-990802 Supplement Technical Guide Colour Television EURO 4 / EURO 4H and EURO 4D Chassis Circuit Explanations 3DQDVRQLF (XURSHDQ 7HOHYLVLRQ 'LYLVLRQ 0DWVXVKLWD (OHFWULF 8. /WG...
  • Page 85 3DQDVRQLF CONTENTS Introduction ............Chapter 1.

  • Page 86: Introduction

    EURO 4H chassis with new simple 100Hz As this supplemental technical guide covers three processing. variants of the EURO 4 chassis, this technical guide has been split into chapters as presented in the EURO 4D IDTV chassis with integrated Digital Video Broadcasting (DVB) terrestial decoder.

  • Page 87: Chapter 1. Common Circuits

    3DQDVRQLF Chapter Common Circuits Geometry Adjustment Large screen CRT’s require an additional circuit which Pin 3 is fed to the inverting input of internal op-amp1, is used for picture geometry adjustment. This while the input via pin 6 is fed to the non-inverting input additional circuit is used to cancel the effects of the of op-amp2.

  • Page 88: Audio Signal Processing (Euro 4 And Euro 4H Only)

    3DQDVRQLF Chapter Common Circuits Audio Signal Processing As with all EURO 4 models, audio processing is and 25 of IC2101 are now fed via the Acoustic provided by the MSP3410 IC2101. The MSP3410 is Feedback (AFB) stage discussed in chapter 1 section designed as a Multi-standard Sound Processor used 3.

  • Page 89: Audio Acoustic Feedback

    3DQDVRQLF Chapter Common Circuits Acoustic Feedback (AN6554) The Euro 4 models which have an additional circuit variations in frequency response, a microphone is named Acoustic Feedback (AFB), is located on the positioned within the speaker enclosure and is used Z-Board and is used to overcome variations in the to monitor the acoustic conditions.
  • Page 90 3DQDVRQLF Chapter Common Circuits 3.1. Acoustic Feedback Processing The audio signals, output from the Multi-standard From this RC network, the left audio speaker signal Sound Processor IC2101 pins 24 and 25 (located on is input via pin 10 of IC2221. Here the feedback the E-Board) are fed via transistors Q2102 and Q2103 microphone signal input at pin 9 and the left speaker via connectors E10 / Z4 pin 1 and 2 to the Acoustic...
  • Page 91 3DQDVRQLF Chapter Common Circuits 3.1.1. Microphone ON/OFF Control to the Z-Board via connectors M7 and Z3 pin 1. Once on the Z-Board the control line is fed to the base This control is used for models which do not have a of two muting transistors Q2201 and Q2202.

  • Page 92: Af Audio Output

    3DQDVRQLF Chapter Common Circuits AF Audio Output Both amplitude controlled audio signals output from The usual negative feedback occurs from pin 11 to pin pins 24 and 25 of IC2101 of the MSP are fed to the 1 and from pin 7 to pin 6 of the I.C. via the R/C network base of transistors Q2102 and Q2103.
  • Page 93 3DQDVRQLF...

  • Page 94: Chapter 2. Euro 4 Supplement

    3DQDVRQLF Chapter EURO 4 Supplement Control and Teletext Processing 1.1. Control Processing supply falls to approximately 4.8V the reset IC IC1105 inputs a reset pulse via pin 54 of the microprocessor IC1101. The following section only highlights changes in control processing which have occurred with the Pin 71 - VProt introduction of new models into the EURO 4 line up, This input is used to detect a fault in the deflection...
  • Page 95 3DQDVRQLF Chapter EURO 4 Supplement 1.1.2. Output Control LOW by Q1101 which is conducting at this point due to the 5V standby supply fed to the base of Q1101 via Pin 45 - 4:3 RGB R1112. Once the supply voltages have become The 4:3 RGB control output from the microprocessor established pin 53 of the microprocessor IC1101 pulls is used to support the display of an RGB picture on...

  • Page 96: Dynamic Automatic Focus

    3DQDVRQLF Chapter EURO 4 Supplement Dynamic Automatic Focus (D.A.F.) 2.1. Introduction connector E4 to the P-Board via connector P4. Once on the P-Board the signal splits into two paths. Euro 4 wide screen models (PK1 and PK2) have an The first path feeds the vertical pulse to the additional circuit provided,...
  • Page 97 3DQDVRQLF Chapter EURO 4 Supplement P-Board DAF Circuit...
  • Page 98 3DQDVRQLF Chapter EURO 4 Supplement 2.3. AN5422K (IC3901) The horizontal and vertical pulses as mentioned horizontal drive signal applied to the gate terminal of earlier are fed to IC3901 pins 13 and 15. Here a Q3905. At switch on Q3911 is biased into conduction vertical and a horizontal drive pulse are produced and by the rising 12V supply line which is fed via R3974 output via pins 3 and 21.
  • Page 99 3DQDVRQLF Chapter EURO 4 Supplement Transistor Q3903 is then used to generate a parabola Here the signal is added to the focus voltage of T551, signal of approximately 5Vpp. This parabola the focus voltage VF2 with the D.A.F. waveform signal waveform is then fed to the cascade connected which is then supplied to the focus terminal on the transistors Q3907, Q3906.
  • Page 100 3DQDVRQLF Chapter EURO 4 Supplement 2.3.1. RGB 4:3 Mode Q580 and pin 45 of the microprocessor IC1101, which pulls the base of Q580 LOW. This results in the On those models which use the VDP IC601 located transistor switching OFF and the relay contact on the E-Board, an additional circuit is required.
  • Page 101 3DQDVRQLF...

  • Page 102: Chapter 3. Euro 4H Supplement

    The following section covers the control processing pin 8. AV2 also allows the input of an S-VHS stage of the new 100Hz Euro 4 chassis which has signal as does AV3 ( wide screen models only ). been introduced into the EURO 4 line up.
  • Page 103 3DQDVRQLF Chapter EURO 4H Supplement Pin 71 - VProt output amplifiers in this I.C. to a greater or lesser extent, thereby limiting the beam current. This input is used to detect a fault in the deflection circuit. This is achieved by using the vertical Where the control limit is exceeded, and the amplifiers synchronisation signal...
  • Page 104 3DQDVRQLF Chapter EURO 4H Supplement 1.1.2. Output Control not changed, the ICs controlled by the I C bus have, these being: Pin 53 - Reset Out To ensure correct operation of the digital ICs, they The following are connected to I C- bus 1: must be started at a specific time in order to permit On the F-Board the VPC IC1501, CIP IC1502,...

  • Page 105: F-Board Processing

    3DQDVRQLF Chapter EURO 4H Supplement F-Board Processing On EURO 4H models the VDP processor IC601 chrominance before the signals are processed by the located on the E-Board has been replaced by an internal comb filter and colour decoder. F-Board. The F-Board contains 4 video processing Component Interface Processor IC1502 ICs, used used to perform a number of functions.
  • Page 106 3DQDVRQLF Chapter EURO 4H Supplement 2.2. Comb Filter Video Processor VPC3215C The VPC3215C is a high quality, single chip video Pin 61 (Vin2) is the input for a composite video signal input via AV1. front end device providing the following features: Digital video processing Pin 62 (Vin1) is the composite video signal which is fed from the tuner stage.
  • Page 107 3DQDVRQLF Chapter EURO 4H Supplement 2.2.2. Adaptive Comb Filter is intended for S-VHS wide bandwidth chrominance. If the adaptive comb filter of the VPC3215C IC1501 The digital CVBS signal fed from the previous is used for luminance chrominance separation, the front-end stage is fed to the 4H adaptive comb filter colour decoder uses the S-VHS processing mode.
  • Page 108 3DQDVRQLF Chapter EURO 4H Supplement 2.3.2. Horizontal Scaler The VPC3215 IC1501 supports this feature using a letterbox detector. The detector is used to detect The horizontal scaler which is fed the 4:2:2 YC black video lines by measuring the signal amplitude signal from the previously discussed stage is used to during active video.
  • Page 109 3DQDVRQLF Chapter EURO 4H Supplement 2.3.4. Output Formatter frequency is programmed by an internal Fast Processor (FP). The final processing stage of the VPC for the luminance and chrominance signals is the formatter 2.3.6. Control stage here the signals are output from the VPC via pins 20-25 / 28-29 for luma and 38-43 / 46-47 for In addition to those signals mentioned above the VPC chroma in 4:2:2 format at 20.25MHz, synchronised by...
  • Page 110 3DQDVRQLF Chapter EURO 4H Supplement 2.4. CIP3250A (IC1502) The CIP IC IC1502 contains the entire circuitry and 36-43 (chroma). required to interface analogue YUV and RGB signals The first stage these signals are fed is the format to a digital YUV signal. The fast blanking signal is used conversion stage used to convert the input signal to control internal switching between the digitised format of 4:2:2 to 4:4:4 format for internal processing.
  • Page 111 3DQDVRQLF Chapter EURO 4H Supplement 2.4.1. Pin Information SDA pin 32 AVO - pin 29 This is the serial data input which is part of the I C bus 1 control line. Input from the VPC IC1501 is the AVO signal which is used to synchronise the active video signal.
  • Page 112 3DQDVRQLF Chapter EURO 4H Supplement 2.5. SDA9401 (IC1503) The SDA9400 and SDA9401 are model dependent, Digital vertical zooming they are both used as a 100Hz high end solution for Digital vertical panning digital TV, which offer the features listed below. However SDA9400 uses...
  • Page 113 3DQDVRQLF Chapter EURO 4H Supplement 2.5.1. Operation with the luminance signal being output from pins 1, 3-7, 63 and 64, while the chrominance signals are The selected digitised luminance and chrominance output via pins 10-17. Here both the luminance and signals output from IC1502 via pins 10-17 (luma) and chrominance signals are fed to IC1504, the final pins 20-27 (chroma) are fed to the input of IC1503.
  • Page 114 3DQDVRQLF Chapter EURO 4H Supplement 2.6. DDP3310B (IC1504) The DDP3310 IC1504 is a single chip digital video RGB Processing deflection processor, designed for high quality Programmable RGB matrix back-end applications in 100Hz TV sets with 4:3 or Additional analogue RGB / fast blank inputs 16:9 picture tubes.The IC contains the entire digital video and deflection processing stages which are as Picture frame generator...
  • Page 115 3DQDVRQLF Chapter EURO 4H Supplement 2.7. Display Processing The luminance and chrominance signals input to the Transient Improvement (DCTI). DDP IC1504 are fed via pins 54-61 (luma) and pins The DCTI stage is used to sharpen the chrominance 43-50 (chroma), synchronised by the horizontal and rise time, which is achieved by applying a correction vertical synchronisation signals input via pins 63 and signal that is calculated by differentiating the colour...
  • Page 116 3DQDVRQLF Chapter EURO 4H Supplement 2.8. RGB Switching Stage The digital RGB signal fed from the Tube Control inserted into the main RGB signal path under the stage, is input to the RGB Switching Stage. Here the control of the fast blanking pulse. The control of white digital RGB signal is converted to analogue RGB, drive, brightness and contrast adjustments being before being output from the DDP IC1504.
  • Page 117 3DQDVRQLF Chapter EURO 4H Supplement 2.9. CRT Measurement and Control EHDP FXUUHQW 6HQVH 5 0$'& 5 5 56: 7XEH 0HDVXUHPHQW &XWRII  :KLWH GULYH 3LFWXUH 0HDVXUHPHQW %HDP &XUUHQW 7XEH 0HDVXUHPHQW The DDP is also equipped with an A/D converter During cut-off measurement the input range of the which is used to perform Tube and Picture measuring A/D converter is set by resistor R603 measurement, this information being fed from the...
  • Page 118 3DQDVRQLF Chapter EURO 4H Supplement 2.9.3. Deflection Processing 2.9.5. Control In addition to these signals mentioned above, the The deflection processing stage of the DDP IC1504 DDP also requires the following: is used to generate the signals for the horizontal and Reset In pin 39 is used during the switch ON vertical drive.

  • Page 119: Colour Output Stage

    3DQDVRQLF Chapter EURO 4H Supplement COLOUR OUTPUT STAGE The Y-Board (TNP8EY018), contains not only the between connector Y5 pins 1 and 3), which is colour output stage, but also scan velocity modulation controlled directly via the collector terminals of stage. transistors Q908, Q909 via resistor R929 which is coupled in parallel to the deflection winding.
  • Page 120 3DQDVRQLF Chapter EURO 4H Supplement 3.3. Tube and Picture Measurement 3.4. BEAM CURRENT LIMITATION Tube and Picture measurements are carried out by The measurement of the beam current as mentioned gating relevant information back via transistors Q351, in the previous section is fed via the Sense input of the Q361 and Q371 to the sense input, pin 17 of the DDP DDP IC1504 pin 17, the result of the measurement IC1504.
  • Page 121 3DQDVRQLF Chapter EURO 4H Supplement Y-Board Schematic...

  • Page 122: Av2 Video Out Switching

    3DQDVRQLF Chapter EURO 4H Supplement AV2 Video Out Switching AV2 video out switching on EURO 4 is performed on This newly combined video signal is then fed to the the H-Board by IC3401. However with the introduction E-Board via connector E15 and is fed to pin 8 of of the F-Board, used on 100Hz EURO 4 models, AV2 IC601.

  • Page 123: Vertical Output

    3DQDVRQLF Chapter EURO 4H Supplement Vertical Output Stage 5.1. LA7876N During vertical sweep, the bootstrap capacitors C456 and C463 are charged up to almost supply voltage via On EURO 4H models the vertical output IC used is the D454 and D458. The output of the pump-up LA7876 which is fed a drive pulse output from the DDP generators at pins 8, 9 and 10 of IC451 are at this IC1504 pins 19 and 20 to the vertical output stage...
  • Page 124 3DQDVRQLF...

  • Page 125: Chapter 4. Euro 4D Supplement

    TV The second path has the A.C. supply being fed operations as on the first generation EURO 4 chassis. via the windings P1/P2 of the standby transformer The second power supply circuit (discussed in chapter 4 Section 2.) located on the W-Board uses the...
  • Page 126 3DQDVRQLF Chapter EURO 4D Supplement The first path sees the supply voltage being The second path the supply takes is via fed via resistor R861 to the standby relay resistor R862 to the base of transistor Q852. RL801 and the relay winding to the collector This supply being regulated by the zener of transistor Q853.
  • Page 127 3DQDVRQLF Chapter EURO 4D Supplement 1.2. Flyback Converter Power Supply The STR-F6654 is a hybrid IC with built-in MOS-FET 1.2.1. General and control IC as well as a separate oscillation circuit. It features a small SIP (Single In-line Package) with The mains A.C.
  • Page 128 3DQDVRQLF Chapter EURO 4D Supplement 1.3. Start Up Circuitry The start-up circuit, consisting of resistors R805 and Once IC801 begins to operate the supply voltage at R814, is used to start and stop operations of the pin 4 is supplied via the rectifying diode D803 and control IC IC801, this is achieved by detecting the smoothing capacitor C816 which is fed from the drive voltage that appears at the Vcc terminal, pin 4.
  • Page 129 3DQDVRQLF Chapter EURO 4D Supplement 1.4. Operation 1.5. Regulation When the internal MOS-FET transistor of IC801 The power supply ON time is controlled by controlling conducts the current flows via the primary winding P1 / the feedback supply to pin 1 of IC801. This is achieved P2 of T801 and IC801 pin 3 (Drain) and pin 2 (source) by the use of the photocoupler D805.
  • Page 130 3DQDVRQLF Chapter EURO 4D Supplement 1.6. Protection Circuitry 1.6.1. Thermal Shut-down In this condition the Vcc input (pin 4) voltage decreases until the the Vcc input reaches the This circuit triggers the latch circuit when the body of shut-down voltage of 10V. At this point pin 4 begins to •...
  • Page 131 3DQDVRQLF Chapter EURO 4D Supplement 1.7. Secondary side On the secondary side the transformer supplies the 1.7.1. Voltage Stabilisation following voltages : The stabilisation of the previously mentioned B+ voltage used to supply the line output stage secondary supplies is performed as follows: 12V and 5V to supply an operating voltage to A 15V supply which is fed from the the TV digital processing ICs.

  • Page 132: Digtal Video Broadcasting Power Supply

    3DQDVRQLF Chapter EURO 4D Supplement DVB Power Supply 2.1. General On the EURO 4D chassis, we see the introduction of by the integrated circuit STR-F6653, IC4801. The an integrated DVB (Digital Video Broadcasting) A.C. mains supply voltage input via connector M10 of decoder used for the processing of digital terrestrial the M-Board is fed via the main TV ON/OFF switch signals.
  • Page 133 3DQDVRQLF Chapter EURO 4D Supplement The DVB power supply relay RL4801 is controlled by normally open relay contact to close. When the relay the DVB microcontroller and transistors Q4852, contact closes the mains A.C. supply is fed to the Q4851. bridge rectifier D4802.
  • Page 134 3DQDVRQLF Chapter EURO 4D Supplement 2.2. Start Up Operation The start-up circuit, which consists of resistors R4802 This supply voltage which is fed from the drive winding and R4803, is used to start and stop operations of the V1 of T4801 is initially unable to provide the supply power supply IC IC4801.
  • Page 135 3DQDVRQLF Chapter EURO 4D Supplement 2.3. Operation 2.4. Regulation The power supply ON time is controlled by controlling the feedback supply to pin 1 of IC4801. This is When the internal FET transistor of IC4801 conducts the current flows via the primary winding P2 / P1 of achieved by the use of the photocoupler D4811 whose conduction is varied in response to the load which is T4801 and IC4801 pin 3 (Drain) and pin 2 (source)
  • Page 136 3DQDVRQLF Chapter EURO 4D Supplement 2.5. Protection Circuitry 2.5.1. Thermal Shut-down 2.5.4. Latch This circuit triggers the latch circuit when the body of The latch circuit is used to keep the output from the • the IC exceeds 140 oscillator low stopping the power supply operating when the over voltage (OVP) and thermal shut-down 2.5.2.
  • Page 137 3DQDVRQLF Chapter EURO 4D Supplement 2.6. Secondary side On the secondary side of transformer T4801 the 32V to supply the digital tuner voltages supplied are as follows: 12V, 5V and 3.3V are used to supply operating Although the secondary voltages are relatively stable voltages to the DVB digital processing ICs.
  • Page 138 3DQDVRQLF Chapter EURO 4D Supplement 2.7. Voltage Stabilisation 2.7.1. 12V Supply The regulator input being connected to the 5V supply via a voltage divider consisting of resistors R4871 / A 14V supply which is fed from the transformer T4801 R4872. is fed to pin 1 of IC4851 which is used to produce a If any load variations are detected by IC4853, the stabilized 12V supply output from pin 3.
  • Page 139 3DQDVRQLF Chapter EURO 4D Supplement 2.8. Secondary Supply Protection On the secondary side of the power supply a number Q4855 conducting pin 2 of IC4852 is then pulled LOW of protection circuits are used which are discussed switching OFF IC4852. below.

  • Page 140: Microprocessor And Teletext Processing

    3DQDVRQLF Chapter EURO 4D Supplement MICROPROCESSOR AND TELETEXT PROCESSING The microprocessor SDA5450 IC1101 used on chassis is the same as EURO 4 , some pin differences EURO 4D chassis, performs the same processing as do occur, these differences being highlighted in the that of EURO 4 which is control and teletext following sections.
  • Page 141 3DQDVRQLF Chapter EURO 4D Supplement 3.1. Microprocessor Stage 3.1.1. Input Control conduct resulting in transistor Q1118 being biased into conduction, feeding a HIGH level to pin 8 of the Pins 3/4 - XIN / XOUT microprocessor IC1101. The internal oscillator of the CPU is synchronised with The ALE control line pin 8 is held HIGH until the supply an external 6MHz quartz crystal X1101 which is voltages have become established, at which time pin...
  • Page 142 3DQDVRQLF Chapter EURO 4D Supplement Pin 58 - Slow1 / Pin 59 Slow2 via resistors R1130, R1129 and R1126 to pin 58 of the microprocessor IC1101. The circuit is designed so that it is possible to switch over to either AV1 or AV2 channels from all The table shown below shows the required voltages programme locations, allowing automatic processing for aspect ratio selection.
  • Page 143 3DQDVRQLF Chapter EURO 4D Supplement Pin 67 - IRef ABL protection During normal operation the beam current is This is a reference current for internal PLL. measured, with the result being input via the sense input of VDP IC601, pin 28. Pin 68 - CVBS In The beam current limitation is carried out via software control with the results of this being used to back off...
  • Page 144 3DQDVRQLF Chapter Common Circuits 3.1.2. Output Control Pin 6 - WR OSD information on screen. The RGB signals being output from the following terminals: This is the Write Enable line used to signal the UART Blue - pin 39, Green - pin 38, Red - pin 37 IC IC1107 when information is going to be written to this device.
  • Page 145 3DQDVRQLF Chapter EURO 4D Supplement Pin 55 - Service LOW level results in Q1013 switching ON and the DVB LED is illuminated. PLEASE NOTE: Even though this following option is Pin 73 - In still available when in Service Mode, the EAROM of This control line output from pin 73 of the the EURO 4D Chassis is 32k bits and the Memory Pack is only 16k bits.
  • Page 146 16k bits. This means that the memory pack is Down load of Country selection. unable to store all the EAROM data. These above features will only work with a Panasonic The following are connected to I C- bus 2 : TV / video combination who are both Q-Link (Project 50+) compliant.
  • Page 147 3DQDVRQLF Chapter EURO 4D Supplement 3.2. Teletext Processing Stage General Programme Signal (VPS). The VPS feature is not used. already briefly mentioned earlier microprocessor performs teletext processing as well Display Timing which is used to ensure that the as Control processing. To perform teletext processing text information is locked to the same timing as the the following elements are required: raster scan.
  • Page 148 3DQDVRQLF Chapter EURO 4D Supplement 3.2.1. Teletext Operation the data is stored in the display RAM until the TTX data is required. To enable teletext processing by the microprocessor When the TTX data is requested the information is IC1101 a CVBS signal is input via pin 68. Here the read out of the Display RAM via the interface and fed signal is fed to the Teletext (TTX) slicer stage, where to the Display Generator.

  • Page 149: Memory Ic (Earom)

    3DQDVRQLF Chapter EURO 4D Supplement MEMORY I.C. (EAROM) Together with the system data for the digital IC’s, The memory location address is then transmitted by customer data is also stored in the EAROM IC1103. the master I.C. (in this case the microprocessor). This address also consists of an 8 bit word whose The stored data includes programme location data reception is again confirmed by an acknowledgement...

  • Page 150: Video Display Processor (Vdp)

    3DQDVRQLF Chapter EURO 4D Supplement Video Display Processor - VDP3120 Although the internal processing of VDP3120, IC601 the chrominance signals are output from pin 13 of has not changed, a full explanation of which can be IC3401 and fed to the VDP, IC601 pin 60. found in the EURO 4 Technical Guide section 17 , the Pin 61 - Vin1 (RFV) input and output processing paths have, these...

  • Page 151: Dynamic Auto Focus (Daf)

    3DQDVRQLF Chapter EURO 4D Supplement Dynamic Automatic Focus (D.A.F.) 6.1. Introduction The first path feeds the vertical pulse to the vertical deflection coil which is fed via connector Euro 4D wide screen models have an additional circuit The second path feeds the vertical signal via the provided, named Dynamic Automatic Focus (D.A.F.), zener diode D3931 and transistor Q3921 where this circuit is used to overcome the problems of poor...
  • Page 152 3DQDVRQLF Chapter EURO 4D Supplement P-Board DAF Circuit...
  • Page 153 3DQDVRQLF Chapter EURO 4D Supplement 6.3. AN5422K (IC3901) The horizontal and vertical pulses as mentioned is fed to the vertical drive stage, the amplitude of the earlier are fed to IC3901 pins 13 and 15. Here a vertical pulse being set by R3927 / R3918 connected vertical and a horizontal drive pulse are produced and to pin 19.
  • Page 154 3DQDVRQLF Chapter EURO 4D Supplement 6.3.1. RGB 4:3 Mode compression and expansion takes place in the horizontal scaler stage within the VDP. However the On those models which use the VDP IC601 located RGB signal which is also fed to and processed by the on the E-Board, an additional circuit is required.
  • Page 155 3DQDVRQLF Chapter EURO 4D Supplement Where a normal wide screen display is processed the short circuiting L590, R590 and C590. The horizontal the horizontal drive signal is fed from the line output signal is again finally fed via coils L595, L591 and L594 transistor Q551, to connector E4.

  • Page 156: Audio Signal Processing

    3DQDVRQLF Chapter EURO 4D Supplement Audio Signal Processing As with all EURO 4 models, audio processing is in the Euro 4 Technical Guide, section 20. provided by the MSP3410 IC2101. The MSP3410 is Although the internal processing of the MSP3410 designed as a Multi-standard Sound Processor used IC2101 has not changed, the input and output in the processing of analogue and digital audio...
  • Page 157 3DQDVRQLF Chapter EURO 4D Supplement 7.1.1. Output Signal Processing Path transistors Q2102 and Q2103 The right and left audio signals are then fed to the Pin 21 - DACA_R Z-Board where the audio signals are processed by the This left channel output is used to provide an Acoustic Feedback (AFB) stage discussed in independently controlled volume for the headphones, chapter 1, section 3.

  • Page 158: Headphone Processing

    3DQDVRQLF Chapter Common Circuits Headphone Processing On the EURO 4D chassis, although not Dolby Pro E-Board), its operation being discussed in section Logic, independant volume control for the headphone 10.1 of the EURO 4 Technical Guide. output is used. This independent volume control is During the ON and OFF periods the mute control provided by the MSP3410 IC2101, which outputs the signal is fed via connectors E22 / M6 pin 4 to the...

  • Page 159: Audio And Video Switching

    3DQDVRQLF Chapter EURO 4D Supplement Audio and Video Switching 9.1. H-Board Overview Analogue:- This option allows the standard analogue TV signals be output via AV2. The audio and video switching circuit which consists Once an analogue TV signal has been selected of two ICs, IC3401 and IC3151 are both located on the you are then free to change to a DVB channel, as H-Board.
  • Page 160 3DQDVRQLF Chapter EURO 4D Supplement 9.2. Video Switching Outline The switching of the video, luminance and inputs, five fixed level outputs and one variable gain chrominance signals is provided by IC3401, output. The switching of this matrix is controlled via TEA6415C.
  • Page 161 3DQDVRQLF Chapter EURO 4D Supplement 9.3. Video Signal Source 9.3.1. Video Switching Inputs output from pin 13. This detection being used to ensure that no interference occurs in any of the Signals input to the video switching IC IC 3401, are subsequent processing paths.
  • Page 162 3DQDVRQLF Chapter EURO 4D Supplement 9.4. Audio Switching Outline The audio switching is performed by IC3151 and right matrix with five inputs and four outputs. TEA6420. This switching matrix has the same features as the TEA6415 except that it contains a left C bus 4 control is via pins 23 and 24.
  • Page 163 3DQDVRQLF Chapter EURO 4D Supplement 9.5. Audio Signal Source 9.5.1. Audio Switching Inputs monitor audio output terminal JK3403 located on the H-Board. Signals input to the audio switching IC IC3151, are applied from a number of sources. These are shown Pin 21 - TV Rin below: The input at pin 21 sees the right audio signal output...

Table of Contents