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6.1 "Superchip" (CSP and DSP combined) - (IC27)
The superchip is the interface between the RF circuitry, the audio circuits
and the digital domain. It also carries out layer 1 signal processing, this
includes data coding/decoding, data interleaving/de-interleaving, error
detection/correction and provides burst generation data. Unlike previous
versions of DSP package which used external static random access memory
(SRAM) devices for data storage of signal processing operations. The
superchip incorporates its own internal 8K * 16 RAM capability to perform
these functions.
The device has the following control functions and connections:-
•
Transmit power control
•
Transmit I and Q outputs
•
Digital Audio Interface
•
Control outputs for the RF Circuit
• RF Synthesiser controls - (IC201)
• 13MHz system clock
I/P:
O/P: The signal TXP (#90) controls the ramp shape from
the RF Power amplifier.
O/P:
TIPI,TINI,TQPI and TQNI (#86-89)
O/P: DAICK, DAIRN, DAIDI and DAIDO (#6-9)
O/P:
VCO_ON (#16) : Power enable for VCO
TX_ON (#17) : Power enable for transmit circuitry
GSM_ON (#18): Power enable for GSM circuitry
PCN_ON (#19) : Power enable for PCN circuitry
PRE_ON (#22) : Power enable for RF pre amplifier
GSM_TX (#23) : Power enable for GSM TX path
PCN_TX (#24) : Power enable for PCN TX path
PUPLO2 (#26) : Power enable for 2nd local Osc
RX_ON1 (#27) : Power enable for RX circuitry
RX_ON2 (#28) : Power enable for RX circuitry
GSM_LNA (#29) : Power enable for GSM RX path
PCN_LNA (#30) : Power enable for PCN RX path
O/P:
SERLT (#12) : Synthesiser data latch enable
SERCK (#13) : Synthesiser data clock
SERDA (#14) : Synthesiser serial data
13MHz (#59)
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