S3.5. Analog Timer Block Diagram - Panasonic DMR-ES20P Service Manual

S3.5. Analog Timer Block Diagram

FRONT(L)P.C.B.
S7503 S7506
CH-UP CH-DOWN
S7504 S7505
PLAY STOP
S7507
REC
Q7504
(FAN MOTOR DRIVE)
FAN MOTOR
M P7503
1
P7503
3
S7001
P7001 P7502
4
POWER
IR7501
S7501
REMOTE CTL.
SENSOR
OPEN/
CLOSE
3 2 1
X SW+5.2V
IC7503
(RESET)
X SW+5.2V 2 VDD OUT 1
IC7505
(FAN MOTOR DRIVE)
X SW +12.5V
1 3 7 5
IC7501
(TIMER)
DIG1 40
DIG4 37
SEG1 41
SEG16 56
SEG17 36
SEG18 35
4 KEY IN3
5 KEY IN2
VPP 57
6 KEY IN1
P SAVE H 2
21 REMOCON
DI P ON H 16
DR P ON H 19
22 P FAIL L
JC P ON H 20
10
QS1
X7501
8MHz
(MAIN CLK)
9 QS2
12 X IN
X7503
32.768KHz
(REAL TIME CLK)
13 X OUT
XRESET 15
FAN PWM
18
OUT
XT MUTE 64
33 FAN LOCK
L1 SWIDE 3
S-8
DP7501
29 1G
14 2G F+ 32
11 3G
4 4G F- 1
TIMER DISPLAY
28 26 24 22 20 19 17 15 13 12 10 9 7 5
X SW+12V
IP7501
IC
1
PROTECTOR
Q7503
POWER ON H
TO
POWER
DR P ON H
BLOCK SECTION
JC P ON H
IC7502
(X RESET)
4 OUT
TO AUDIO
XT MUTE
BLOCK SECTION
FROM VIDEO
L123 SWIDE
BLOCK SECTION
DMR-ES20P/PC
Analog Timer Block Diagram
T7501
9
DISPLAY
3
REGULATOR
8
5
1
2
Q7502
P SAVE
CONTROL
VDD 5 XSW+5.2V