Analog Timer Block Diagram - Panasonic DMR-EZ17P Service Manual

DMR-EZ17P

11.5. Analog Timer Block Diagram

S7502 S7503
PLAY STOP
S7506
S7507
CH-UP CH-DOWN
S7501
REC
FRONT (L) P.C.B.
S7002
POWER
S7504
RESET
S7505
OPEN/
CLOSE
IC7514
(RESET)
X SW+5.2V 2 VDD
IC7512
(X RESET)
5 VDD
JW7501
1
IR7501
REMOTE CTL.
SENSOR
3 2
IC7501
(TIMER)
G1 44
G4 47
16
KEY1
S1 48
S18 65
17 KEY2
18
KEY3
VPP 90
37 RST KEY
P SAVE H 75
OUT 1 29 P FAIL L
DI P ON H 23
8
OUT 4 X RESET
JC P ON H 7
DR P ON H 71
1
25 IR
XRESET 8
XT MUTE 100
11 10MHz IN
X7501
10MHz
(MAIN CLK)
10 10MHz OUT
L123 SWIDE 19
38
DP7501 T7501
F+
32 9
G1-G4 TIMER
S1-S18 DISPLAY
F-
1 8
DISPLAY
REGULATOR
5
X SW+12V
IP7501
IC
1 2
PROTECTOR
Q7503
DI P ON H
TO
POWER
JC P ON H
BLOCK SECTION
DR P ON H
IC7512
(X RESET)
4 OUT
TO AUDIO
XT MUTE
BLOCK SECTION
FROM VIDEO
L123 SWIDE
BLOCK SECTION
DMR-EZ17P
Analog Timer Block Diagram
3
1
Q7502
P SAVE
CONTROL
VDD 5 XSW+5.2V