Main(Pre/Rec) Schematic Diagram - JVC GR-D370UC Schematic Diagrams

MAIN(PRE/REC) SCHEMATIC DIAGRAM

0
HID3
HID
TO CPU
PBH
RECH
MONI_CHG
TL3501
TO MAIN IF(CN102)
ENV_OUT
TO MAIN IF(CN102),
ATFI
PARAGON
ATF_GAIN
TO PARAGON
REC_ADJ
REC_CTL
VREF_1.1
TO PARAGON
AGC_OUT
VRB_AGC
VRB_ATF
TO MAIN IF(CN102),
ATFI
PARAGON
REF_CLK
TO PARAGON
REC_DATA
REC_CLK
REG_4.8V
REG_3.1V
TO PARAGON,REG
REG_2.5V
GND
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
2-17(No.YF124)
MAIN(PRE/REC)
1
R3516
L3502 NQLC32M-100X
0Ω
L3505 OPEN
L3501 NQR0602-001X
L3503 NQR0602-001X
48
C3517
0.01
PB_OUT
49
C3527
220p
AGC_IN
50
C3518
0.01
AGC_CTL
51
AGC_DET
52
C3519
0.001
PB_GND
53
AGC_OUT
54
C3520
0.01
AGC_BUFF_I
55
C3521
REG_1.1V
0.1
56
AGC_BUFF_O
57
VRB_AGC
58
C3522
4.7
MAIN_GND
59
ATF_GAIN
60
C3523
0.01
VCA_OUT
61
C3524
0.01
ATF_IN
62
C3525
4.7 VRB_ATF
63
ATF_OUT
64
1
R3517
56k
R3518
6.2k