Main(Video) Schematic Diagram - JVC GR-D370UC Schematic Diagrams

MAIN(VIDEO) SCHEMATIC DIAGRAM

DCO0
DCO1
DCO2
DCO3
TO PARAGON DYO0
DYO1
DYO2
DYO3
OUTH
TO MAIN IF(CN104),
OUTV
CPU,PARAGON
TO PARAGON
CLK27A
TO CPU VOI_IN
VOI_OUT
TO CPU,PARAGON
VOI_CLK
TO CPU
VIF_CS
TO CPU,OP DRV T_F_V_RST
VC0
VC1
VC2
VC3
TO CPU
BLKA
BLKB
BLKC
OSD_HD
TO CPU,PARAGON
OSD_VD
DOT_CLK
TO CPU PSCTL
TL3202
ANA_IN_H
TL3203
TO PARAGON ASPECT
ASPECT
L3201
NQR0602-001X
REG_4.8V
REG_3.1V
TO PARAGON REG_1.7V
GND
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
HDCVF
VDCVF
TL3201
CSYNC
VDOUT
SCANMODE
C3206 0.01
VDD(C)
VSS
RESVD
IC3201
JCP8055FP-2
RESHD
SDOUT
SDIN
SCLK
CS
C3207 0.01
VDD(I)
VSS
RST
L3203 L3204
NQR0602-001X 10µ
L3202
NQR0602-001X
C3219
1
T T
C3204 C3205
10/6.3 47/6.3
C3202 C3203
0.1 0.1
(No.YF124)2-15
L3701
10µ
C3701
10
SCANEN
C3215 0.1
AVDD
AVSS C3718
0.1
C3213 0.1
VREF1
YSOUT
C3212 0.1
COMP1
ABAR1
YCOUT
R3204 820
R3701
IREF1 150
AVSS
AVDD
COUT
VREF2
CBOUT
C3210 0.1
COMP2
ABAR2
R3208
820
R3202 R3203
27k 15k
R3722
150
IC3202
MM3143BN-X
3.1V
VIN VOUT
GND
STBY NC
R3725
150
C3218
1
2-16(No.YF124)
0 1 MAIN(VIDEO)
R3703
OPEN
C3706
OPEN
Q3701
OPEN
C3712
100/4
C3710
22/4
IC3702
NJM2562F1-X
VIN VSAG
5 4
GND VOUT
OPEN
R3721 C3717 D3701
OPEN 0.1 UMZ6.8EN-W
VCC PSCTL
R3720 0
1 2 3
R3728
150
yf124_y10598001a_rev0.1
TL3204
Y_OUT TO MAIN IF(CN101)
Y_OUT
R3708
68
TO MAIN IF(CN101,102)
V_OUT
TL3205
C_OUT TO MAIN IF(CN101)
C_OUT
LCD_G
LCD_B TO MONI/VF
LCD_R
VDCVF
TO MAIN IF(CN103),
MONI/VF
HDCVF
TO MAIN IF(CN103)
HRP