Main(Audio) Schematic Diagram - JVC GR-D370UC Schematic Diagrams

MAIN(AUDIO) SCHEMATIC DIAGRAM

0 1 MAIN(AUDIO)
R2602 R2601
2.2k 2.2k
L2603
NQR0599-001X
C2602
OPEN
INT/R
INT_GND
TO INT MIC
(CN2601) INT_GND
L2602
INT/L
NQR0599-001X
C2601
OPEN
L2601
NQR0599-001X
TO MAIN IF SPK+
(CN103) SPK-
DIFFERENCE LIST
SYMBLE D1S3(P3) D1S5(P2) D1S5(P3)
IC2201 AK4664VQ AK4660VQ AK4664VQ
R2201 OPEN 470k OPEN
µ
C2201 OPEN 0.1 OPEN
SYMBOL LIST
LAST VACANT
2200 R 35 5, 14~16, 18~30, 32
(MAIN) C 35 6~8, 11, 12, 15, 16, 19~22, 25~28, 30~32
Q 2
2400 R 8 4~6
(REG)
C 7
L 3
Q 3 2
2600 R 19 3~6,11~19
(INT MIC) C
24 7, 8, 14~22
L 3
C
2650 56 51~54
(EXT MIC)
L
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
L2403
10µ
OPEN
Q2401
OPEN
R2401
OPEN OPEN
C2401 R2408
T
R2202
560k
R2201
#
C2201
#
36
C2624
10p
R2610
22k
37 PREOR
C2612
1 R2608 2.2k
38 PRENR
C2656
0.01µ
39 EXTR
C2604
0.022
C2606 0.0047
40 INTR
41 MGND
42 MVDD
C2407
10µ
43 MPWR
C2613
1
44 MRF
C2603
0.022
C2605 0.0047
45 INTL
C2655
0.01µ
46 EXTL
C2611
1 R2607 2.2k
47 PRENL
R2609
22k
48 PREOL
C2623
10p
1
D2S7(P3)
AK4664VQ
OPEN
OPEN
NO MOUNT
1
29,33~35 1
R2212
2 2.7
8 1
1 C2217
0.1
1
(No.YF124)2-11
C2405
C2203
0.1
1
35 34 33 32 31 30 29 28 27 26 25
C2214 0.1
RIN1 24
C2210
ROUT1 23
C2213 0.1
LIN1 22
C2209
LOUT1 21
DVSS 20
C2406
10µ
DVDD 19
IC2201
#
LRCK2 18
MCLK2 17
BCLK2 16
SDTI2 15
SDTO1/SDTO2 14
R2217
SDTI1 13
C2229
OPEN
2 3 4 5 6 7 8 9 10 11 12
C2235 C2234 C2233
OPEN OPEN OPEN
L2402
R2213 10µ
2.7 C2403
10µ
C2218
0.1
2-12(No.YF124)
L2401
10µ
Q2403
2SC4617/RS/-X
R2402
4.7k
C2402
C2404 R2403
10µ
10/6.3 18k
T
R2209
22k
R2207 R2211
820
1 56k
R2208
22k
R2206
R2210
820
1 56k
3 6 R2235
OPEN
R2407
10 5 2
4 1
Q2202
OPEN
10
yf124_y20398001a_rev0.1
REG_4.8V
REG_3.1V
GND
AU_SIG/R
TO MAIN IF
(CN101)
AU_SIG/L
S_SHUT
AIDAT/AIDAT2
AODAT
TO PARAGON
AILRCK
AIMCK
AIBCK
TO MAIN IF(CN103),
AU_LV_CLK CPU,MONI/VF
AUDIO_CS TO CPU
TO MAIN IF(CN103),
AU_LV_OUT
CPU,MONI/VF
BUZZER
PD_L
TO CPU
A_MUTE
L_MUTE