IBM Power 780 Technical Overview And Introduction page 181

Figure 4-3 shows a POWER7 chip, with its memory interface, consisting of two controllers
and four DIMMs per controller. Advanced memory buffer chips are exclusive to IBM and help
to increase performance, acting as read/write buffers. On the Power 770 and Power 780, the
advanced memory buffer chips are integrated into the DIMM that they support.
POWER7
POWER7
Core
256 KB L2
256 KB L2
32 MB L3 Cache
256 KB L2 256 KB L2
POWER7 POWER7
Core
Memory Controller
Port
Buffer Chip Buffer Chip
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DIMM DIMM
DIMM
Figure 4-3 POWER7 memory subsystem
Memory page deallocation
Although coincident cell errors in separate memory chips are a statistic rarity, IBM POWER
processor-based systems can contain these errors by using a memory page deallocation
scheme for partitions that are running IBM AIX and IBM i operating systems, and also for
memory pages owned by the POWER Hypervisor. If a memory address experiences an
uncorrectable or repeated correctable single cell error, the service processor sends the
memory page address to the POWER Hypervisor to be marked for deallocation.
Pages used by the POWER Hypervisor are deallocated as soon as the page is released.
In other cases, the POWER Hypervisor notifies the owning partition that the page should be
deallocated. Where possible, the operating system moves any data that is currently contained
in that memory area to another memory area and removes the page (or pages) that are
associated with this error from its memory map, no longer addressing these pages. The
operating system performs memory page deallocation without any user intervention and is
transparent to users and applications.
The POWER Hypervisor maintains a list of pages that are marked for deallocation during the
current platform initial program load (IPL). During a partition IPL, the partition receives a list of
all the bad pages in its address space. In addition, if memory is dynamically added to a
partition (through a dynamic LPAR operation), the POWER Hypervisor warns the operating
system when memory pages are included that need to be deallocated.
POWER7 POWER7
Core Core
256 KB L2 256 KB L2
256 KB L2 256 KB L2
POWER7 POWER7
Core Core
Memory Controller
Port Port Port
Buffer Chip Buffer Chip
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DIMM
DIMM DIMM
Chapter 4. Continuous availability and manageability
Core
Core
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DIMM
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