Yamaha 01x Service Manual page 135

H G
BLOCK DIAGRAM 003
MLN2
mLAN2 I/F
CN6 (100P)
MIDI IN/OUT (5 port)
MIDI (UART)
I/F
16bit
PLL-Lock
CPU bus
I/F Async (Hold)
ACTV
ROOT
mLAN-Word Clock Direction
mLAN-Word Clock Slected
/RESET
Tx Digital Audio (24ch) (max)
WCK (Fs)
Digital MCK (256Fs)
Audio
I/F
MCK (256Fs @Fs = 44.1 – 48kHz, 128Fs @ Fs = 2 – 96kHz))
Rx Digital Audio (16ch)
WCK (Fs)
+5V
+3.3V
F E
Packet-Master/Slave
48
CPU Bus @mLAN-NC1's CPU core
29
33
PLL-Response
31
Exp. I/O port Async (Hold)
32
21
ACTV
IC14A (100P)
35 36
Packet-Master/Slave
40
ROOT
*(CPLD)-#1
93
90 BCK (64Fs)
DRIVER
IC14C (100P)
*(CPLD)-#1
*Digital Audio Format : 24bit/MSB-First/Left Justfied/2ch@line
D C
Xtal
20MHz
X1
Up to 40MHz by Internal PLL
110, 111
PHY – LINK I/F
mLAN-NC1 SCLK <49.512MHZ>
33 3
[MIDI Packet]
EEPROM
IC2
14, 15
IC8 (256P) 5, 6 16K
IC9 (8P)
GUID/Module Name/Config.
3.072MHz, 48kHz for MIDI Packet
232
89
ICLK <24.576MHz>
DRIVER
IC14B (100P)
*(CPLD)-#1
6
PCA (SYT-Match)
4
90
57
mLAN-PH2 PCB (Divider Out) 5
58
88
YTS440B-F
[AUDIO Packet]
106
512fs
IC7 (208P)
3
69
56
PLL-Lock
101
76
Packet-Master/Slave
B
Xtal
24.576MHz
X2
Up to 393.216MHz by Internal PLL
1
29, 30
CN2
42–45
PHY
MD8408B
IEE1394 (S400)
2
IC10 (64P)
38–41 CN3
ACTV
LD4
ACTIVE
1
REGULATOR
+5V
IC4
3
+3.3V
PLL
TLC2932
PHASE 6
COMPARATOR
PLL-Response
LPF
IC2 (14P)
Low Jitter/Vari Pttch Following
TR1
VCO 1
CV
28CA1-8825603-003
A
O1X
1
2
3
4
5
6
5
1