Clock - TC Electronic System 6000 Basic Operation

Ultimate multichannel processing platform
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Frame - E1 to E4
This page holds the User group parameters for all four
Engines. Selecting User group parameters is done from the
Engine pages. Values can be altered from both the Engine
Edit pages and the page displayed above. Press the
parameter you wish to assign to the Fader located below.

Clock

Clock Mode
To be able to successfully clock your system you must
select between two basic ranges of Sample Rates. We call
these ranges Normal and Double mode. Double mode
covers Sample Rates 88.2 and 96kHz, Normal mode
covers 32, 44.1 and 48kHz. If incorrect mode is selected
when trying to lock, no lock status can be obtained.
Normal Rate:
32, 44.1 or 48kHz are supported.
When Internal mode is selected 44.1 or 48kHz are
supported
Double Rate:
88.2 or 96kHz are supported.
FRAME - SYSTEM - MAIN
Clock Master
Select the Clock source for the complete Mainframe,
including all Engines and all I/O's.
Select between:
Internal, Wordclock, AES 1-2, 3-4, 5-6 or 7-8.
A lock up to an external source will take approx. 7 sec.
It is not necessary to have the Physical Input
routed to an Engine Input to have the clock accepted.
Internal Clock Rate
The internal Clock Rate can be set to 44.1 or 48kHz when
Clock Mode is set to Normal and 88.2 or 96kHz when
Clock Mode is set to Double.
Locked Clock Rate
The Clock Rate to which the Mainframe is currently locked.
If the incoming Sample Rate is +/- 0.2% away from 32,
44.1, 48, 88.2 or 96kHz the Sample Rate will be shown
with an added "!" to indicate that the Sample Rate is
inaccurate.
Detected Sample Rate
This is a read-only parameter indicating the actual incoming
Sample Rate. The tolerance of this detection is +/- 10Hz.
An incoming Sample Rate of 44.056kHz will be detected as
approx. 44.06kHz and the system indicates the Locked
Clock Rate 44.100kHz.
The system will lock to and reject jitter at any Sample Rate
between:
• 30 - 34kHz
• 42.5 - 45.5kHz
• 46.5 - 48.5kHz
• 85 - 91kHz
• 93 - 97kHz
Sample Slip
Monitors the Clock status of the incoming AES/EBU
Inputs and indicates whether the incoming Clock is in sync
with the mainframe Clock settings. Three states of
incoming clock can be indicated.
Locked
The Input is in Sync with the Mainframe.
Sample Slip
The Input is out of sync with the Mainframe. Check that
there is only one Master Clock source in your setup.
Not Available
Indicates no connection available.
13

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