Radio Shack TRS-80 Service Manual page 26

MODEL III 10 BUS
The Mode! III 10 Bus was designed to allow easy and conve·
nient interfacing of 10 deviccs to the Modcl Ill. The 10 Bus
supports
ali
the signals necessary
to
implement a devicil
compatible to the 2-80's 10 structure. That is:
Addresses:
AG to A7 allow selection of up
to 256 t input and 256
output devices.
(If
external 10 is enabled.)
tports 80H to I3FFH are reserved lor Sy$lem use.
Data:
Dgg to DB7 allow transfer of 8-bit data onlo the pro-
cessor data bus if external 10 is enabled.
Control lines:
a. IN- - 2-80 signal specifying that an input is in pro-
gress. Gated with lORa.
b. OUT' -
Z ·80 signal specifying that an output is in
progress. Gated with 10 RO.
c. RESET· - system reset signal.
d. 10BUSINT- input to the CPU signaling an an
interrupt from an 10 Bus device if 10 Bus interrupts
are enabled.
e. 10BUSWAIT- - input to the CPU wait line allowing
10 Bus devices to force wait states on the Z·80 if
external 10 is enabllKt.
f. EXTIOSEL - - input to CPU which switches the
10 Bus data bus transceiver and allows an INPUT
instruction to read
10
Bus data.
g. M1·and lORa- - standardZ-80signals.
The address line, data line, and control lines a to c and e to
9
are enabled only when the ENEXIO bit in EC is set to a one.
To enable 10 interrupts. the ENIOBUSINT bit in CPU
10PORT E0 (output port) must be a one. However, even it
disabled tram generating Interrupts, the status at the
10BUSINT" line can still read on the appropriate bit of CPU
10PORT E0.lInput port).
See Model 111 Port Bit assignment for ports tiFF. GEC. and
o ElJ on attached sheets.
The ModeJ III CPU board is fullv pfotected from "foreign 10
devices" in that all the 10 Bus signals are buffered and can
be
disabled under software control. To attach and usc an 10
device on the 10 Bus. certain requirements (both hardware
& sohware) must be met.
For input port dcvice use, you muSI enable extern ill 10
devices bv writing to pan 0ECH
WIth
bit
4
on in the user
softwilre. This will enable the data bus addrcss IIn~s,
ilnd
control signals to the 10 Bus
edg~
connector. When the
input device is selected the ha~dware w II acknowledge by
assert.ng EXTIOSE L' low. ThIS :;witches tile datil bus
trilnsceiver and allows the CPU to read the conlelllS
of
the 10
bus data lines.
see
Figure
3
for the timing. EXTIOSEL· can
be generated bv NANOing IN and the 10
port
IIddress.
Output
1>0'
r device use is the same as input port device in use
in that the el<ternal 10 devices mU$t be en"blcd bV writing to
port OECH with bit
4
on in the user software. in
the same
fashion.
For either input or output devices. the 10BUSWAIT' control
line can be used in the normal way 10' synchronizing slow
devices
10
tne
CPU. Note that since dynamic memories afC
used in the Model III. the wait hne should
be
used with
caution. Holding the CPU in a w"it slllte tal 2mSl'C or more
may cause loss of memory contents since refresh 's inhibited
during this time. It is recommended that the IOBUs\''VAIT'
line be held active no more than 500 ~sec with a 25% duty
cycle.
The Model III will support Z·BO mode 1 interrupts. A RAM
jump lable is supported bv the lEVEL II BASIC ROMS and
the Usel ,"ust supplv the address of his interrupt service
routine bv writing this address to locations 403E, and 4133F.
When an interrupt occurs the program will be veCtOled to the
user supplied address if 10 Bus interruplS have been enabled.
To enable 10 Bus interrupts the user must set bit 3 of Port
0EGH.
19